Abstract: Methods for forming a semiconductor devices are provided. A plasma pre-treatment operation is performed on a photoresist pattern formed over a material disposed over a substrate, and reduces critical dimensions (CDs) of features of the photoresist pattern to a greater extent at a central portion of the substrate than at outer portions of the substrate, thereby forming a treated pattern with a gradient of CDs. The material is then etched using the treated pattern as a photomask. An overetch operation that tends to reduce CDs of the etched features of the material to a greater extent at outer portions of the substrate than at the central portion of the substrate, is employed. The plasma pre-treatment operation is designed in conjunction with the overetch characteristics and, in combination, the operations produce etched features having CDs with a high degree of uniformity across the substrate.

Abstract: Methods for forming a semiconductor devices are provided. A plasma pre-treatment operation is performed on a photoresist pattern formed over a material disposed over a substrate, and reduces critical dimensions (CDs) of features of the photoresist pattern to a greater extent at a central portion of the substrate than at outer portions of the substrate, thereby forming a treated pattern with a gradient of CDs. The material is then etched using the treated pattern as a photomask. An overetch operation that tends to reduce CDs of the etched features of the material to a greater extent at outer portions of the substrate than at the central portion of the substrate, is employed. The plasma pre-treatment operation is designed in conjunction with the overetch characteristics and, in combination, the operations produce etched features having CDs with a high degree of uniformity across the substrate.

Abstract: The disclosure generally relates to a method for method for plasma etching a substrate in a plasma reactor comprising positioning the substrate on an electrostatic chuck inside the plasma reactor; supplying a DC voltage to the chuck, the DC voltage forming an electrostatic charge buildup on the substrate; plasma etching the substrate; disconnecting the DC voltage to the chuck; and counteracting the electrostatic charge buildup on the substrate by discharging a varying RF signal within the chamber.

Abstract: A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.

Abstract: The disclosure generally relates to a method for method for plasma etching a substrate in a plasma reactor comprising positioning the substrate on an electrostatic chuck inside the plasma reactor; supplying a DC voltage to the chuck, the DC voltage forming an electrostatic charge buildup on the substrate; plasma etching the substrate; disconnecting the DC voltage to the chuck; and counteracting the electrostatic charge buildup on the substrate by discharging a varying RF signal within the chamber.

Abstract: A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.