Abstract: A method of making a semiconductor device includes forming a plurality of first gate structures on a substrate, wherein each of the plurality of first gate structures continuously extending in a first direction over a first doped region and a second doped region, the second doped region has an opposite dopant type from the first doped region, an interface of the first region and the second region exists in a space between adjacent first gate structures, adjacent gates are separated from each other in a second direction. The method includes forming a silicide structure on the substrate, wherein the silicide structure comprises a main body and a silicide extension, the silicide extension extends into the space between adjacent gate structures and across the interface between the first region and the second region. The method includes forming an isolation structure between the first region and the second region.

Abstract: A method of biasing a substrate includes electrically connecting a silicide structure to a bias voltage supply. The method further includes conducting a bias voltage received by the silicide structure to a silicide extension extending from a main body of the silicide structure, wherein the silicide extension extends between adjacent gate structures of a plurality of first gate structures. The method further includes transferring the bias voltage from the silicide extension into a doped region of a substrate below the adjacent gate structures of the plurality of first gate structures.

Abstract: A method includes fabricating a first-type active-region structure and a second-type active-region structure, fabricating a first gate-conductor intersecting the first-type active-region structure, and fabricating a first terminal-conductor having a first width and a second terminal-conductor having a second width. Each of the first terminal-conductor and the second terminal-conductor is adjacent to the first gate-conductor and intersects the first-type active-region structure. The second width is smaller than the first width by a predetermined amount. The method also includes forming a first via-connector that is in conductive contact with the first terminal-conductor, and fabricating a first power rail intersecting the first terminal-conductor and conductively connected to the first terminal-conductor through the first via-connector.

Abstract: An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.

Abstract: A method of fabricating an IC includes: forming first and second arrays of active-region structures extending between first and second vertical zone-boundaries, the first vertical zone-boundary being a boundary of a first keep-out zone, and the second vertical zone-boundary being a boundary of a second keep-out zone; forming first-side boundary cells aligned with the first vertical zone-boundary, including: forming a first-side boundary cell that includes: a first ESD device region including a first ESD protection circuit; and a first pick-up region; and forming second-side boundary cells aligned with the second vertical zone-boundary, including: forming a second-side boundary cell that includes: a second ESD device region including a second ESD protection circuit.

Abstract: A device includes: first and second power rails; first and second active regions; a first source/drain (S/D) conductor, wherein: the first S/D conductor is conductively connected to the first active region and the first power rail, and is in a layer between the first active region and the first power rail; a second S/D conductor, wherein: the second S/D conductor is at a same level as the first S/D conductor, the second S/D conductor is conductively connected to the first active region and is spaced apart from the first power rail, and the first S/D conductor is wider than the second S/D conductor; and a first gate between the first S/D conductor and the second S/D conductor, wherein: the first gate, the first S/D conductor, and the second S/D conductor are components of a first transistor at the first active region.

Abstract: A built-in self-tester (BIST) of a semiconductor device including: an input/output (I/O) circuit including an output buffer and an input buffer, an output of the output buffer being coupled at an I/O terminal to an input of the input buffer, the I/O terminal being configured to receive or provide an external I/O signal; one or more resistive-network cell regions arranged to affect a reference current received at the I/O terminal; and a switching arrangement configured to selectively couple the one or more resistive-network cell regions alternatively to a first reference voltage during a first phase or a second reference voltage during a second phase, the switching arrangement being further configured to determine electrostatic discharge (ESD) damage to metal-oxide-semiconductor (MOS) transistors included in the semiconductor device based on (1) phase and (2) an output signal of the input buffer

Abstract: An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.

Abstract: A method of biasing a substrate includes electrically connecting a silicide structure to a bias voltage supply. The method further includes conducting a bias voltage received by the silicide structure to a silicide extension extending from a main body of the silicide structure, wherein the silicide extension extends between adjacent gate structures of a plurality of first gate structures. The method further includes transferring the bias voltage from the silicide extension into a doped region of a substrate below the adjacent gate structures of the plurality of first gate structures.

Abstract: A semiconductor device includes a first doped region in a substrate, wherein the first doped region has a first dopant type. The semiconductor device further includes a second doped region in the substrate, wherein the second doped region has a second dopant type opposite the first dopant type. The semiconductor device further includes a silicide structure on the substrate, wherein the silicide structure includes a main body and a silicide extension. The semiconductor device further includes a plurality of first gate structures on the substrate, wherein a space between adjacent gate structures of the plurality of first gate structures includes a first area and a second area, the silicide extension extends into the first area, the first doped region is in the substrate below the first area, and the second doped region is in the substrate below the second area.

Abstract: An integrated circuit includes an array of first-type active-region structures and an array of second-type active-region structures extending in a first direction between a first vertical zone-boundary of a first keep-out zone and the second vertical zone-boundary of a second keep-out zone. The integrated circuit also includes an array of first-side boundary cells aligned with the first vertical zone-boundary and an array of second-side boundary cells aligned with the second vertical zone-boundary. In the array of first-side boundary cells, a first-side boundary cell has a first ESD protection circuit and a pick-up region. In the array of second-side boundary cells, a second-side boundary cell has a second ESD protection circuit.

Abstract: A semiconductor device includes a first doped region in a substrate, wherein the first doped region has a first dopant type. The semiconductor device further includes a second doped region in the substrate, wherein the second doped region has a second dopant type opposite the first dopant type. The semiconductor device further includes a silicide structure on the substrate, wherein the silicide structure includes a main body and a silicide extension. The semiconductor device further includes a plurality of first gate structures on the substrate, wherein a space between adjacent gate structures of the plurality of first gate structures includes a first area and a second area, the silicide extension extends into the first area, the first doped region is in the substrate below the first area, and the second doped region is in the substrate below the second area.