Abstract: An electronic device includes at least one terminal formed on the electronic device. The electronic device also includes at least one of a semiconductor device, an integrated circuit chip, and a computer. A seamless conductive mesh is formed on at least one surface of the electronic device. The conductive mesh is in electrical contact with the terminal. The terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit. The electronic device also may include a pattern having traces formed on at least two surfaces where each of the traces includes a continuous loop of conductive material is formed on at least two surfaces. The electronic device also may include a first plurality of conductive loops formed on the electronic device that are continuous and surround the electronic device in a first direction and a second plurality of conductive loops formed on the electronic device that are continuous and surround the electronic device in a second direction.

Abstract: A method of fabricating an electronic circuit including forming a first depression on a first surface of a first wafer and forming a second depression on the first surface of the first wafer. The second depression is adjacent the first depression and separated from the first depression by a wall. The method further includes locating an actuator on the wall and attaching a first surface of a second wafer to the first surface of the first wafer to cover the first and second depressions. A first portion of the second wafer and the first depression define a first reservoir to contain a first chemical, and a second portion of the second wafer and the second depression define a second reservoir to contain a second chemical.

Abstract: A method including positioning an electronic device proximate a second device, the electronic device including at least one of a semiconductor device, an integrated circuit chip, and an electronic substrate, and the second device activatable to form a conductive pattern on the electronic device. The method further includes activating the second device to form the conductive pattern and forming the conductive pattern on at least two surfaces of the electronic device. The conductive pattern includes one or more than one conductive trace. Each conductive trace includes a conductive material and is continuous between at least two surfaces of the electronic device. Each conductive trace is formed by controlling relative movement of the electronic device and the second device during activation of the second device.

Abstract: A method of forming an anti-tamper mesh on an electronic device. The method includes forming at least one terminal on the electronic device and forming a conductive mesh on at least one surface of the electronic device, wherein the conductive mesh is in electrical contact with the terminal, and wherein the terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit.

Abstract: A semiconductor device. The device includes a substrate and an integrated circuit chip. The device also includes an electrically or thermally reactive layer located between a top surface of the substrate and a bottom surface of the integrated circuit chip, wherein the reactive layer is positioned such that detection of tampering causes the reactive layer to be electrically or thermally energized such that the semiconductor device is at least partially destroyed.

Abstract: A semiconductor chip includes a first integrated circuit chip and a depression substrate attached to the integrated circuit chip, wherein the integrated circuit chip and the depression substrate define a cavity therebetween. The semiconductor chip also includes a stress sensitive material located in the cavity and a chemical located in the cavity, wherein detection of tampering causes a reaction by the chemical such that the semiconductor chip is at least partially destroyed.

Abstract: A semiconductor chip includes a first integrated circuit chip and a depression substrate attached to the integrated circuit chip, wherein the integrated circuit chip and the depression substrate define a cavity therebetween. The semiconductor chip also includes a stress sensitive material located in the cavity and a chemical located in the cavity, wherein detection of tampering causes a reaction by the chemical such that the semiconductor chip is at least partially destroyed.

Abstract: A method of forming an anti-tamper mesh on an electronic device. The method includes forming at least one terminal on the electronic device and forming a conductive mesh on at least one surface of the electronic device, wherein the conductive mesh is in electrical contact with the terminal, and wherein the terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit.

Abstract: A semiconductor device. The device includes a substrate and an integrated circuit chip. The device also includes an electrically or thermally reactive layer located between a top surface of the substrate and a bottom surface of the integrated circuit chip, wherein the reactive layer is positioned such that detection of tampering causes the reactive layer to be electrically or thermally energized such that the semiconductor device is at least partially destroyed.

Abstract: A method for forming connections within a multi-layer electronic circuit board 10. In one non-limiting embodiment, the method includes selectively forming air bridges over portions of the circuit board 10 and selectively collapsing the air bridges with a metallurgical bonding tool, effective to interconnect layers of the circuit board 10.

Abstract: An ultrasonic wirebonder has a horn and a transducer for vibrating the horn at a predetermined frequency. A magnet affixed to the horn generates a magnetic field. A coil coupled to the magnet has an output signal induced from the magnetic field moving relative to said coil. A filtering means filters the output signal from the coil to determine the reliably of the ultrasonic bond. An output device is used to monitor the output signal and determine whether the bond is reliable.

Abstract: An apparatus for testing an integrated circuit includes a bond substrate having a location for an integrated circuit. The location on the bond substrate has a plurality of traces around each location. A first fixture holds the bond substrate in a fixed relation to first fixture and holds the integrated circuit in a fixed relation to the first fixture and the bond substrate. A wirebonder forms wirebonds between the traces and the bond pads. An electrical tester provides electrical signals from the traces to the bond pads to verifying the operation of the integrated circuit. A second fixture lifts the bond substrate while the integrated circuit remains held to the first fixture. A vibrator vibrates the first fixture in relation to the second fixture so that the wirebonds are broken at a predetermined location near the bond pad.

Abstract: Method for fabricating an undercoated chip electrically interconnected to a substrate. The method includes the initial step of depositing a predetermined quantity of a liquid undercoat material onto the chip or the substrate. The method continues with the step of interconnecting the chip to the substrate so as to form an electrical interconnection bond therebetween. Finally, the method concludes with the step of heating, reflowing and curing the undercoat material during or after the step of electrically interconnecting the chip to the substrate.

Abstract: A test apparatus for testing a know-good die integrated circuit is disclosed. The test apparatus uses conductive straps extending across trenches. The straps align with bond pads on the integrated circuit. When the bond pads are brought into contact with the straps, the straps exert a counterforce in the opposite direction to ensure a good electrical contact while testing the integrated circuit.

Abstract: A process for bonding a flip chip (20) to a substrate (22) comprising positioning the flip chip (20) above the substrate (22). The flip chip (20) has an active face provided with conductive bumps so that its active face is oriented toward the substrate (22). The flip chip (20) is placed on the substrate (22) so that the bumps align with a bonding pattern on the substrate (22). An ultrasonic horn (30) is lowered having a flat surface onto a back side of the flip chip (20). Force is applied through the ultrasonic horn (30) to the back side of the flip chip (20), which is normal to the substrate (22) so that minimal lateral displacement of the flip chip (20) and the substrate (22) results. The ultrasonic horn (30) is then activated while the force is applied so that the ultrasonic energy is isothermally transferred across the flip chip (20) to the substrate (22) and a diffusion bond is created therebetween.

Abstract: Provided is a method and apparatus for electrically detecting the location of bond failure and wire breakage occurring during tensile strength testing of a wire sample having first and second bond foots affixed to respective first and second support pads. The method and apparatus monitors the voltage levels of first and second electrically conductive probes. The first probe has a primary lead in electrical contact with the first support pad and a secondary lead in electrical contact with the first bond foot. Similarly, the second electrically conductive probe has a primary lead in electrical contact with the second support pad and a secondary lead in electrical contact with the second bond foot. Voltage detection circuitry is provided in electrical contact with the first and second probes for detecting the voltage level at each of the respective primary and secondary leads to generate the respective corresponding output signals.