Abstract: A particle beam lithography system and method of blanking a beam such as a particle or other beam. The system may include a frequency divider adapted to convert a master clock signal at a first frequency into an integral number N of waveforms at a second frequency, a reference device adapted to provide a fixed threshold reference signal, a sequencer adapted to provide N sets of data, a blanking circuit for each of the waveforms for creating a blanking signal for each of the waveforms, and a logic circuit for combining each of the blanking signals from each of the blanking circuits. The blanking circuit may include a digital to analog converter adapted to receive one of the N sets of data from the sequencer and to generate a variable threshold reference signal and a window comparator adapted to receive one of the waveforms, the fixed threshold reference signal, and the variable threshold reference signal and to generate a blanking signal.

Abstract: A particle beam lithography system and method of blanking a beam such as a particle or other beam. The system may include a frequency divider adapted to convert a master clock signal at a first frequency into an integral number N of waveforms at a second frequency, a reference device adapted to provide a fixed threshold reference signal, a sequencer adapted to provide N sets of data, a blanking circuit for each of the waveforms for creating a blanking signal for each of the waveforms, and a logic circuit for combining each of the blanking signals from each of the blanking circuits. The blanking circuit may include a digital to analog converter adapted to receive one of the N sets of data from the sequencer and to generate a variable threshold reference signal and a window comparator adapted to receive one of the waveforms, the fixed threshold reference signal, and the variable threshold reference signal and to generate a blanking signal.

Abstract: A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator.