Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically tuning circuit elements. One aspect includes a variable capacitance device. The device includes a first capacitor, a first switch, a second capacitor, a second switch, and control circuitry. The control circuitry is configured to adjust respective capacitances of the first and second capacitors by causing a first control signal to be applied to the first-switch control terminal for a duration of time in response to detecting a zero voltage condition across the first switch, and by causing a second control signal to be applied to the second-switch control terminal for the duration of time in response to detecting a zero voltage condition across the second switch.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically tuning circuit elements. One aspect includes a zero voltage switching device including a switch, a first comparator, a second comparator and a controller. The switch includes a first terminal, a second terminal, and a control terminal. The first comparator includes a first input terminal electrically connected to the second terminal of the switch and a second input terminal electrically connected to the first terminal of the switch. The second comparator includes a first input terminal electrically connected to a reference voltage and a second input terminal electrically connected to the control terminal of the switch. The controller is configured to: detect a zero voltage condition across the switch, and, in response, cause a control signal to be applied to the control terminal of the switch.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically tuning circuit elements. One aspect includes a variable capacitance device. The device includes a first capacitor, a first switch, a second capacitor, a second switch, and control circuitry. The control circuitry is configured to adjust respective capacitances of the first and second capacitors by causing a first control signal to be applied to the first-switch control terminal for a duration of time in response to detecting a zero voltage condition across the first switch, and by causing a second control signal to be applied to the second-switch control terminal for the duration of time in response to detecting a zero voltage condition across the second switch.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically tuning circuit elements. One aspect includes a variable capacitance device. The device includes a first capacitor, a first switch, a second capacitor, a second switch, and control circuitry. The control circuitry is configured to adjust respective capacitances of the first and second capacitors by causing a first control signal to be applied to the first-switch control terminal for a duration of time in response to detecting a zero voltage condition across the first switch, and by causing a second control signal to be applied to the second-switch control terminal for the duration of time in response to detecting a zero voltage condition across the second switch.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically tuning circuit elements. One aspect includes a variable capacitance device. The device includes a first capacitor, a first switch, a second capacitor, a second switch, and control circuitry. The control circuitry is configured to adjust respective capacitances of the first and second capacitors by causing a first control signal to be applied to the first-switch control terminal for a duration of time in response to detecting a zero voltage condition across the first switch, and by causing a second control signal to be applied to the second-switch control terminal for the duration of time in response to detecting a zero voltage condition across the second switch.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting characteristics of an input signal. One aspect includes a first finite impulse response (FIR) filter, a second FIR filter, and a controller coupled with the first and second FIR filters. The first FIR filter receives an input signal and a first reference signal. The first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal. The second FIR filter receives the input signal and a second reference signal. The second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal. The controller determines characteristics of the input signal based on the first and second mixed signals.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically tuning circuit elements. One aspect includes a variable capacitance device. The device includes a first capacitor, a first switch, a second capacitor, a second switch, and control circuitry. The control circuitry is configured to adjust respective capacitances of the first and second capacitors by causing a first control signal to be applied to the first-switch control terminal for a duration of time in response to detecting a zero voltage condition across the first switch, and by causing a second control signal to be applied to the second-switch control terminal for the duration of time in response to detecting a zero voltage condition across the second switch.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting characteristics of an input signal. One aspect includes a first finite input response (FIR) filter, a second FIR filter, and a controller coupled with the first and second FIR filters. The first FIR filter receives an input signal and a first reference signal. The first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal. The second FIR filter receives the input signal and a second reference signal. The second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal. The controller determines characteristics of the input signal based on the first and second mixed signals.

Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.

Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.