Patents by Inventor Curt Schnarr

Curt Schnarr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital frequency locked delay line
    Patent number: 8437428
    Abstract: A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: May 7, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Curt Schnarr
  • DIGITAL FREQUENCY LOCKED DELAY LINE
    Publication number: 20120063551
    Abstract: A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.
    Type: Application
    Filed: November 17, 2011
    Publication date: March 15, 2012
    Inventor: Curt Schnarr
  • Digital frequency locked delay line
    Patent number: 8064562
    Abstract: A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 22, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Curt Schnarr
  • DIGITAL FREQUENCY LOCKED DELAY LINE
    Publication number: 20100142660
    Abstract: A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 10, 2010
    Inventor: Curt Schnarr
  • Digital frequency locked delay line
    Patent number: 7664216
    Abstract: A device includes a signal generator having a delay locked circuit for providing a of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Curt Schnarr
  • High accuracy current mode duty cycle and phase placement sampling circuit
    Patent number: 7514991
    Abstract: A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: April 7, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Curt Schnarr
  • High accuracy current mode duty cycle and phase placement sampling circuit
    Publication number: 20080309375
    Abstract: A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 18, 2008
    Inventor: Curt Schnarr
  • Digital frequency locked delay line
    Publication number: 20060029175
    Abstract: A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a selector for selecting an enable signal from a range of signals formed by the output signals. The device further includes a transceiver circuit in which the transceiver circuit uses the enable signal for data processing.
    Type: Application
    Filed: August 5, 2004
    Publication date: February 9, 2006
    Inventor: Curt Schnarr