Abstract: The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

Abstract: An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.

Abstract: A configurable multi-protocol transceiver implemented in an integrated circuit (“IC”) includes configurable deskew circuitry. The transceiver has various configurable deskew settings to facilitate effectively adapting transmit and/or receive communications corresponding to a selected one of a plurality of high-speed communication protocols and/or adapt to different implementations in which a deskew block addresses either just static skew or both static and dynamic skew. Configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. Configurable circuitry is adapted to control a deskew character transmit insertion frequency. A programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition.

Abstract: The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

Abstract: Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations.

Abstract: An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract: An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract: Receiver circuits in serial lanes each generate a synchronous clock signal that is aligned with a master clock signal to allow synchronous transfer of data onto the master clock domain without corruption. A serial-to-parallel converter circuit in each receiver circuit converts a serial data signal into parallel data signals in response to one of the synchronous clock signals. Phase detection circuitry generates an indication of a phase shift based on a phase offset between the synchronous and master clock signals. A clock signal generation circuit provides an adjustment to a phase of the synchronous clock signal based on the indication of the phase shift. The serial-to-parallel converter circuit adjusts positions of bits indicated by the parallel data signals based on the adjustment to the phase of the synchronous clock signal.

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract: Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Abstract: A PLD comprises a substrate, an array of programmable logic elements formed in the substrate, a first columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to a first side of the substrate, and at least a second columnar interface coupling to the array of logic elements and extending in the substrate substantially parallel to the first columnar interface. The interfaces illustratively provide a plurality of interconnects, control circuits and one or more of driver circuits, rebuffering circuits, signal conditioning circuits, deskewing circuits, clock synchronization circuits, power management circuits, testing/debugging circuits, partial reconfiguration circuits, multi-plexing circuits, pipelining circuits and storage circuits. The PLD is mounted on an interposer so that its interfaces electrically couple to electrically conducting paths on the interposer.

Abstract: In accordance with an embodiment of the invention, precision control of error injection may be accomplished by way of synchronous error signals accompanying data transfers along various pipeline stages of a data path. The synchronous error signals may be used to trigger error events in a given protocol logic block (i.e. in a given sub-component of the data path). The protocol logic block is configurable to determine whether any action is to be taken upon the assertion of the error signal. Multiple error events may be triggered as the data signal (and its accompanying synchronous error signal) passes through pipelined functions of the data path so as to create complex error conditions. In addition, deterministic handling of created errors may be accomplished using a loopback path with bypassable blocks on both forward and reverse transformations. Other embodiments, aspects and features are also disclosed.

Abstract: On programmable device, each layer of a programmable interface, for a protocol which has a protocol stack including at least a physical layer, a data link layer and a transaction layer, is selectably bypassable. When a layer is bypassed, all other layers downstream of that layer also are bypassed. In addition, the interface may be divided into different clock domains running at different clock rates, reflecting clock rates within the programmable device and outside the programmable device. Layers may be bypassed to allow a user to substitute a custom layer in programmable logic, or to substitute an updated layer for debugging purposes.

Abstract: Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-phased, candidate clock signals are used one after another in order of increasing phase to clock the DDR circuitry. Adjacent bits in the training data that should be equal-valued are captured by the DDR circuitry and compared. Any candidate clock signal that causes the bits thus compared to be unequal is flagged as having phase close to edges in the data. The approximate phase of data edges is thereby indicated by the phase (or phases) of the candidate clock signal (or signals) causing the bits compared as described above to be unequal.