Patents by Inventor Curtis C. Hainds

Curtis C. Hainds has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6594604
    Abstract: A system for determining scattering parameters (S-parameters) characterizing the behavior of a network applies a wideband stimulus signal containing multiple signal components as input to the network. The system then measures incident and reflected waveforms at all of the network's ports, digitizes and converts the measured waveforms from time domain to frequency domain data, and then computes the S-parameters values for each frequency component of interest from the frequency domain data for that frequency. The system also determines its own error coefficients (E-coefficients) for each frequency of interest from data collected during a sequence of measurements in response to either a sinusoid or a wideband signal and adjusts the computed S-parameter values accordingly.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: July 15, 2003
    Assignee: Credence Systems Corporation
    Inventors: Donald M. Metzger, David B. Marshall, Curtis C. Hainds
  • Patent number: 6288454
    Abstract: A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: September 11, 2001
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, Curtis C. Hainds, Charles W. Jurgensen, Brian R. Lee
  • Publication number: 20010004729
    Abstract: A system for determining scattering parameters (S-parameters) characterizing the behavior of a network applies a wideband stimulus signal containing multiple signal components as input to the network. The system then measures incident and reflected waveforms at all of the network's ports, digitizes and converts the measured waveforms from time domain to frequency domain data, and then computes the S-parameters values for each frequency component of interest from the frequency domain data for that frequency. The system also determines its own error coefficients (E-coefficients) for each frequency of interest from data collected during a sequence of measurements in response to either a sinusoid or a wideband signal and adjusts the computed S-parameter values accordingly.
    Type: Application
    Filed: February 14, 2001
    Publication date: June 21, 2001
    Inventors: Donald M. Metzger, David B. Marshall, Curtis C. Hainds
  • Patent number: 6136662
    Abstract: A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: October 24, 2000
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, Curtis C. Hainds, Charles W. Jurgensen, Brian R. Lee