Patents by Inventor Curtis C. Wollbrink
Curtis C. Wollbrink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10761995Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.Type: GrantFiled: April 26, 2019Date of Patent: September 1, 2020Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, Jeffrey A. Stuecheli, Michael S. Siegel, William J. Starke, Curtis C. Wollbrink, Kenneth M. Valk, Lakshminarayana Arimilli, John D. Irish
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Patent number: 10554347Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: GrantFiled: November 27, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen, Curtis C. Wollbrink
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Publication number: 20190332549Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.Type: ApplicationFiled: April 26, 2019Publication date: October 31, 2019Inventors: BARTHOLOMEW BLANER, JEFFREY A. STUECHELI, MICHAEL S. SIEGEL, WILLIAM J. STARKE, CURTIS C. WOLLBRINK, KENNETH M. VALK, LAKSHMINARAYANA ARIMILLI, JOHN D. IRISH
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Patent number: 10396944Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: GrantFiled: September 19, 2017Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen, Curtis C. Wollbrink
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Publication number: 20190089496Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: ApplicationFiled: November 27, 2017Publication date: March 21, 2019Inventors: CHAD M. ALBERTSON, ERIC J. CAMPBELL, NICHOLAS J. OLLERICH, CHRISTOPHER W. STEFFEN, CURTIS C. WOLLBRINK
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Publication number: 20190089495Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: ApplicationFiled: September 19, 2017Publication date: March 21, 2019Inventors: CHAD M. ALBERTSON, ERIC J. CAMPBELL, NICHOLAS J. OLLERICH, CHRISTOPHER W. STEFFEN, CURTIS C. WOLLBRINK
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Patent number: 10216653Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.Type: GrantFiled: October 3, 2017Date of Patent: February 26, 2019Assignee: International Busiess Machines CorporationInventors: Lakshminarayana Baba Arimilli, Yiftach Benjamini, Bartholomew Blaner, Daniel M. Dreps, John David Irish, David J. Krolak, Lonny Lambrecht, Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Kenneth M. Valk, Curtis C. Wollbrink
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Publication number: 20180095905Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.Type: ApplicationFiled: October 3, 2017Publication date: April 5, 2018Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: LAKSHMINARAYANA BABA ARIMILLI, YIFTACH BENJAMINI, BARTHOLOMEW BLANER, DANIEL M. DREPS, JOHN DAVID IRISH, DAVID J. KROLAK, LONNY LAMBRECHT, MICHAEL S. SIEGEL, WILLIAM J. STARKE, JEFFREY A. STUECHELI, KENNETH M. VALK, CURTIS C. WOLLBRINK
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Patent number: 9684618Abstract: A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.Type: GrantFiled: April 11, 2014Date of Patent: June 20, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elizabeth A. McGlone, Brian T. Vanderpool, Jeffrey B. Williams, Curtis C. Wollbrink
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Patent number: 9563591Abstract: A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.Type: GrantFiled: March 6, 2014Date of Patent: February 7, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elizabeth A. McGlone, Brian T. Vanderpool, Jeffrey B. Williams, Curtis C. Wollbrink
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Patent number: 9292460Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.Type: GrantFiled: February 25, 2013Date of Patent: March 22, 2016Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 9292462Abstract: Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.Type: GrantFiled: May 22, 2013Date of Patent: March 22, 2016Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Publication number: 20150254202Abstract: A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.Type: ApplicationFiled: April 11, 2014Publication date: September 10, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elizabeth A. MCGLONE, Brian T. VANDERPOOL, Jeffrey B. WILLIAMS, Curtis C. WOLLBRINK
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Publication number: 20150254200Abstract: A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.Type: ApplicationFiled: March 6, 2014Publication date: September 10, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elizabeth A. MCGLONE, Brian T. VANDERPOOL, Jeffrey B. WILLIAMS, Curtis C. WOLLBRINK
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Patent number: 9122604Abstract: Method for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination.Type: GrantFiled: February 25, 2013Date of Patent: September 1, 2015Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Nicholas V. Tram, Curtis C. Wollbrink
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Patent number: 9087162Abstract: The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.Type: GrantFiled: February 26, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 9043526Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.Type: GrantFiled: June 20, 2012Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 8949499Abstract: The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.Type: GrantFiled: June 20, 2012Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Publication number: 20140351484Abstract: Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.Type: ApplicationFiled: May 22, 2013Publication date: November 27, 2014Applicant: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 8898359Abstract: Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.Type: GrantFiled: February 26, 2013Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink