Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Abstract: A circuit card assembly is provided for use in testing a system wherein the circuit card assembly employs a surface mount device such as a field programmable gate array. The circuit card assembly includes severable traces on a bottom surface of the assembly connecting pairs of near and far vias. The severable traces and the pairs of near and far vias allow the circuit card assembly to be selectively re-worked to accommodate changes to the design of the surface mount device. Hence, a new circuit card assembly need not be designed and fabricated each time the design or programming of the surface mount device is changed. The circuit card assembly includes a network of interconnection paths wherein each path to or from a pin terminal area of the circuit card assembly passes along at least one severable trace between at least one pair of near and far vias along the bottom surface of the assembly.