Abstract: A cab assembly is disclosed for use with a machine having a frame. The cab assembly may include an operator cab with a first side and a second side, a plurality of cab mounts connecting the operator cab to the frame, and a hydraulic cylinder connected at one end to the operator cab and at an opposing end to the frame. The plurality of cab mounts may be selectively disconnected from the operator cab to allow the hydraulic cylinder to tilt the operator cab toward the first side or the second side of the operator cab.

Abstract: One embodiment of the invention sets forth a hardware-based physics processing unit (PPU) having unique architecture designed to efficiently generate physics data. The PPU includes a PPU control engine (PCE), a data movement engine and a floating point engine (FPE). The PCE manages the overall operation of the PPU by allocating memory resources and transmitting graphics processing commands to the FPE and data movement commands to the DME. The FPE includes multiple vector processors that operate in parallel and perform floating point operations on data received from a host unit to generate physics simulation data. The DME facilitates the transmission of data between the host unit and the FPE by performs data movement operations between memories internal and external to the PPU.

Abstract: A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.

Abstract: A PPU-enhanced computer system is provided including a Physics Processing Unit (PPU), a Graphics Processing Unit (GPU), a Central Processing Unit (CPU) and a main memory, wherein the system creates an animation from application data stored in the main memory by data communication between the GPU, PPU, CPU and main memory. The system may include a memory controller and a chip set connecting the bus structure to the CPU and GPU through an I/O interface and connecting the PPU though a bus structure. The PPU may be a separate processing core logically grouped with the CPU and GPU processing cores. In this preferred embodiment, the CPU, GPU and PPU receive data from a common L2 cache and/or a main system memory.

Abstract: A PPU-enhanced system is described in which a Physics Processing Unit (PPU) and a Graphics Processing Unit (GPU) are connected with the system.

Abstract: A system, such as a PC, incorporating a dedicated physics processing unit adapted to generate physics data for use within a physics simulation or game animation. The hardware-based physics processing unit is characterized by a unique architecture designed to efficiently calculate physics data, including multiple, parallel floating point operations.

Abstract: A hardware-based physics processing unit having unique architecture designed to efficiently calculate physics data.

Abstract: A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.

Abstract: A method and device for controlling bandwidth distribution through a switch fabric is provided wherein a plurality of line cards and processor cards are connected through a switch fabric for parallel processing of transmission requests, along with the provision of transmission “credits” allowing for transmitting additional data bytes during a given cycle, which provides efficient and speedy bandwidth distribution, as well as resolution of output contentions. The processors maintain a credit balance which allows flexibility in granting transmission requests to accommodate transmission scheduling and “bursty” transmissions. Processors on both of the line cards and the processor cards normalize the data transmission requirements for both inputs and outputs connected by the switch fabric. Smoothing of data transmission is provided using a time-weighted buffer.

Abstract: A system for attaching electrical contacts to the conductive ends of wires preferably provides simultaneous sorting operations, wherein different contacts from separate batches are simultaneously sorted in consecutive order; preselection operations, wherein contacts stuck together are removed; simultaneous holding operations, wherein presorted contacts from each batch are accumulated in separate, automatically resupplied queues, for rapid subsequent retrieval by the operator; pneumatic transporting operations, wherein contacts are rapidly retrieved from any queue selected and prealigned opposite the crimping jaws of a crimping unit; and two-step crimping operations, wherein prealigned contacts are quickly gripped by partially closed crimping jaws, in the first step, in preparation for the second step of wire end insertion and full crimping.

Abstract: A system for attaching electrical contacts to the conductive ends of wires preferably provides simultaneous sorting operations, wherein different contacts from separate batches are simultaneously sorted in consecutive order; preselection operations, wherein contacts stuck together are removed; simultaneous holding operations, wherein presorted contacts from each batch are accumulated in separate, automatically resupplied queues, for rapid subsequent retrieval by the operator; pneumatic transporting operations, wherein contacts are rapidly retrieved from any queue selected and prealigned opposite the crimping jaws of a crimping unit; and two-step crimping operations, wherein prealigned contacts are quickly gripped by partially closed crimping jaws, in the first step, in preparation for the second step of wire end insertion and full crimping.

Abstract: A coherent phase detector using a frequency discriminator for reducing a frequency encoded signal to baseband, thereby avoiding the necessity of generating a coherent RF phase reference signal. A baseband processor is provided to compensate for error components arising in the frequency discriminator output. The baseband processor includes feedback loops for DC level correction and automatic gain correction. A novel scheme is also described for reducing the influence of interbit crosstalk on the operation of the baseband processor.

Abstract: In a convolutional code decoder, a current received input corresponds to a last data state of a received sequence. Path metrics, respective correlations of the received sequence to each of a limited number of possible sequences, are determined to choose the "correct" possible sequence. Decoding then proceeds by known means. The current input addresses "look-up" memories, each associated with a possible input data state and providing a "branch metric address" output. "Update" memories, each associated with one of the data states, are each addressed by path metrics of prior sequences which can enter its associated state and by one "branch metric address." In functional effect, each "update" memory adds a separate branch metric to update each prior path metric leading into each state. Path metrics for the limited number of possible sequences are thus provided. An indication of which updated path metric is larger for each state and its value are output from each "update" memory.