Abstract: A high-voltage filter for an alternating-current (AC) to direct current (DC) power adapter of the type having a rectifier providing an internal ground and a high voltage DC, the high voltage DC coupled to drive a DC-DC converter providing a power adapter output, the high voltage filter coupled to filter the high voltage DC, has a first capacitor coupled between the high-voltage DC and an intermediate node. A second capacitor is coupled between the intermediate node and the internal ground. A source follower transistor has a drain coupled to the high-voltage and a source coupled to the intermediate node, with gate coupled to a reference supply. In a particular embodiment, the reference supply has a resistor coupled between the high voltage DC and the gate of the source follower, and at least one zener diode coupled between the gate of the source follower and internal ground.

Abstract: A phase locked loop system has a voltage-controlled variable-load ring oscillator (VLCO) that operates in a frequency band determined by a selected load on each stage of the ring oscillator. Each stage of the VLCO has multiple load selection transistors, each coupled to a load capacitor. Apparatus is provided for driving the load selection transistors according to a load configuration; and apparatus is provided for determining an operating load configuration such that a period of a divided reference signal approximately matches a period of a divided VLCO signal with the VLCO control voltage input clamped to a reference voltage. Once the load configuration is set, the loop is allowed to lock. In a particular embodiment, devices are provided for slowly tweaking the VLCO load to help keep the VLCO operating near an optimum control voltage despite drift of circuit parameters with temperature or time.

Abstract: A power supply system has a full-wave rectifier feeding through an inductor having inductance between one and ten millineries to an energy storage capacitor; and a DC-to DC converter coupled to receive power from the energy storage capacitor. The inductor is configured to provide a peak voltage at the energy storage capacitor greater than a peak voltage at the output of the full-wave rectifier. In an embodiment, the DC-DC converter is a buck-type DC-DC downconverter.

Abstract: A high-voltage filter for an alternating-current (AC) to direct current (DC) power adapter of the type having a rectifier providing an internal ground and a high voltage DC, the high voltage DC coupled to drive a DC-DC converter providing a power adapter output, the high voltage filter coupled to filter the high voltage DC, has a first capacitor coupled between the high-voltage DC and an intermediate node. A second capacitor is coupled between the intermediate node and the internal ground. A source follower transistor has a drain coupled to the high-voltage and a source coupled to the intermediate node, with gate coupled to a reference supply. In a particular embodiment, the reference supply has a resistor coupled between the high voltage DC and the gate of the source follower, and at least one zener diode coupled between the gate of the source follower and internal ground.

Abstract: A phase locked loop system has a voltage-controlled variable-load ring oscillator (VLCO) that operates in a frequency band determined by a selected load on each stage of the ring oscillator. Each stage of the VLCO has multiple load selection transistors, each coupled to a load capacitor. Apparatus is provided for driving the load selection transistors according to a load configuration; and apparatus is provided for determining an operating load configuration such that a period of a divided reference signal approximately matches a period of a divided VLCO signal with the VLCO control voltage input clamped to a reference voltage. Once the load configuration is set, the loop is allowed to lock. In a particular embodiment, devices are provided for slowly tweaking the VLCO load to help keep the VLCO operating near an optimum control voltage despite drift of circuit parameters with temperature or time.

Abstract: An off-chip driver circuit having a set of input terminals and an output terminal, a pull-up transistor having a controllable path connected between a first power supply and the output terminal of the off-chip driver circuit, a pull-down transistor having a controllable path connected between a second power supply and the output terminal of the off-chip driver circuit, a first controllable path for applying a first voltage at one of the input terminals to a control terminal of the pull-up transistor, the first controllable path functioning in response to voltages at the output terminal below a first value, a second controllable path for applying a second voltage greater than the first voltage to the control terminal of the pull-up transistor, the second controllable path functioning in response to voltages at the output terminal above the first value.

Abstract: A mixed signal phase locked loop is optimized for fast settling and low noise sensitivity. To this end, this device has a digital wide range delay line and a low gain per stage adjust. When first activated, the loop calibrates the digital delay line to its nominal delay characteristic. This delay line, together with the linear low gain per stage adjust, constitutes the internal oscillator of the phase locked loop. After achieving nominal delay, the oscillator uses the low gain per stage adjust to lock to a desired reference or a submultiple thereof. According to the preferred embodiment, the loop locks its internal 125 MHz oscillator to a 25 MHz reference. After achieving lock, the loop performs synchronous data recovery by locking to an incoming data stream, instead of the internal reference, and performing bit framing. In case of losing lock, the phase locked loop of the present invention is capable of recalibrating itself and regaining lock in under 3 microseconds.

Abstract: A high-speed receiver/latch is implemented by incorporating a differential amplifier/comparator directly into the feedback loop of a latch function. Both transparent and edge-triggered variants are possible. The resulting circuit is capable of extremely high-speed operation by virtue of very small setup time and small propagation delay.

Abstract: An output driver for an integrated circuit reduces noise generation within the circuit by maintaining di/dt at a low value.

Abstract: A CMOS integrated circuit chip includes a conventional high voltage section and a low voltage section. An on-chip voltage regulator develops a second or pseudo substrate potential at a node that is regulated to a level that is the sum of the thresholds for NMOS and PMOS devices below the V.sub.DD potential. The low voltage section is connected between V.sub.DD and the second substrate potential node. The low voltage section is, therefore, always operated at optimum voltage regardless of device threshold voltage variations that are encountered in CMOS manufacturing. This means that even though the integrated circuit includes a low voltage section, it can be operated over the normal CMOS voltage range as if it contained only high voltage devices.