Patents by Inventor Curtis L. Harbert

Curtis L. Harbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selective trim and wafer testing of integrated circuits
    Patent number: 6872582
    Abstract: A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the sample parameters are measured and if the die passes the sample parameters the die is good and repeat the steps of determining if the die is within specification and measuring the sample parameters until a die fails the measurement test or requires a trimming and if a die fails a measurement test or requires trimming perform 100 percent test and trim.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: March 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Rex W. Pirkle, Curtis L. Harbert, George Reeves
  • Selective trim and wafer testing of integrated circuits
    Publication number: 20030169064
    Abstract: A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the sample parameters are measured and if the die passes the sample parameters the die is good and repeat the steps of determining if the die is within specification and measuring the sample parameters until a die fails the measurement test or requires a trimming and if a die fails a measurement test or requires trimming perform 100 percent test and trim.
    Type: Application
    Filed: January 15, 2003
    Publication date: September 11, 2003
    Inventors: Rex W. Pirkle, Curtis L. Harbert, George Reeves