Patents by Inventor Curtis Lapadat

Curtis Lapadat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for improving stuck-at fault detection in large scale integrated circuit testing
    Patent number: 6185713
    Abstract: A bus holder for coupling to an integrated circuit bus driven by a plurality of tri-state devices. The bus holder has a bidirectional port and first and second test ports. Logic circuitry coupled between the respective ports is configured such that application of a logic 0 to the first test port causes the bidirectional port to drive whatever logic value is applied to that port; application of a logic 1 to the first test port and application of a logic 0 to the second test port pulls the bidirectional port down to a logic 0; and, application of a logic 1 to both the first and second test ports pulls the bidirectional port up to a logic 1.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: February 6, 2001
    Assignee: PMC-Sierra Ltd.
    Inventors: Alan Nakamoto, Kris Iniewski, Monika Swic, Curtis Lapadat, Larrie Simon Carr
  • Built-in test scheme for a jitter tolerance test of a clock and data recovery unit
    Patent number: 5835501
    Abstract: A jitter test system for a clock and data recovery unit (CRU) is comprised of a data generating apparatus, apparatus for clocking the data generating apparatus with a jittered clock, apparatus for applying a stream of data generated by the data generating apparatus that has been jittered by the jittered clock to an input of the CRU, and apparatus for detecting a bit error rate of a data signal output from the CRU.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: November 10, 1998
    Assignee: PMC-Sierra Ltd.
    Inventors: Kamal Dalmia, Andre Ivanov, Brian Donald Gerson, Curtis Lapadat