Abstract: The present invention provides an improved frequency doubling circuit, with adjustable phase offset. Briefly, rather than using the traditional equations cos (2?t)=cos 2(?t)?sin 2(?t) and sin(2?t)=2 sin(?t)cos(?t), the quadrature output signals are generated utilizing mixers, each having two input signals, separated in phase by the same offset. This minimizes the effects of the non-linearities introduced by the mixer, which therefore reduces amplitude mismatch between the quadrature signals. Also, the phase offset of the quadrature output signals can be tuned and calibrated using a phase shifting circuit. This phase shifting circuit realizes a tuning range of approximately 5° in programmable steps. This combination of circuits can be used to minimize the amplitude mismatch and phase errors, thereby reducing the amplitude of and interference caused by transmission of the image frequency to the receivers input.

Abstract: The present invention provides an improved frequency doubling circuit, with adjustable phase offset. Briefly, rather than using the traditional equations cos (2?t)=cos 2(?t)?sin 2(?t) and sin(2?t)=2 sin(?t)cos(?t), the quadrature output signals are generated utilizing mixers, each having two input signals, separated in phase by the same offset. This minimizes the effects of the non-linearities introduced by the mixer, which therefore reduces amplitude mismatch between the quadrature signals. Also, the phase offset of the quadrature output signals can be tuned and calibrated using a phase shifting circuit. This phase shifting circuit realizes a tuning range of approximately 5° in programmable steps. This combination of circuits can be used to minimize the amplitude mismatch and phase errors, thereby reducing the amplitude of and interference caused by transmission of the image frequency to the receivers input.

Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.

Abstract: A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges.

Abstract: A 1.1 GHz fully integrated GaAs MESFET active inductor is presented. Both the inductance and loss resistance are tunable with the inductance independent of series loss tuning. The measured loss resistance is tunable over a −10 &OHgr; to +15 &OHgr; range with a corresponding change in inductance of less than 10% at 100 MHz and less than 4% for frequencies above 500 MHz for capacitive tuning. The inductance is tunable from 65 nH to 90 nH. The measured loss resistance is shown to be dc bias voltage tunable over a 0 to +10 &OHgr; range with an inductance tunable from 55 nH to 110 nH, with negligible interaction between loss resistance and inductance for frequencies from 100 MHz to 1.1 GHz. Several embodiments a using MESFETs and MOSFETs are described. A negative impedance converter is included to achieve increased bandwidth in all circuit realizations. Considerably larger bandwidths can be achieved depending on the fabrication technology employed and the intended application of the circuit.