Abstract: A cache memory controller in a computer system, such as a multicore processing system, provides compression for writes to memory, such as an off-chip memory, and decompression after reads from memory. Application accelerator processors in the system generate application data and requests to read/write the data from/to memory. The cache memory controller uses information relating location parameters of buffers allocated for application data and sets parameters to configure compression and decompression operations. The cache memory controller monitors memory addresses specified in read requests and write requests from/to the first memory. The requested memory address is compared to the location parameters for the allocated buffers to select the set of parameters for the particular application data. Compression or decompression is applied to the application data in accordance with the selected set of parameters. The data size of the data transferred to/from memory is reduced.

Abstract: A cache memory controller in a computer system, such as a multicore processing system, provides compression for writes to memory, such as an off-chip memory, and decompression after reads from memory. Application accelerator processors in the system generate application data and requests to read/write the data from/to memory. The cache memory controller uses information relating location parameters of buffers allocated for application data and sets parameters to configure compression and decompression operations. The cache memory controller monitors memory addresses specified in read requests and write requests from/to the first memory. The requested memory address is compared to the location parameters for the allocated buffers to select the set of parameters for the particular application data. Compression or decompression is applied to the application data in accordance with the selected set of parameters. The data size of the data transferred to/from memory is reduced.

Abstract: An H-bridge circuit formed from two sub-circuits coupled to each other by a load network across a respective load node of each of the sub-circuits. Each sub-circuit of the two sub-circuits comprises a depletion mode upper transistor with a second electrode coupled to a first electrode of a lower transistor. The load node of the sub-circuit is disposed between the second electrode of the upper transistor and the first electrode of a lower transistor. There is a first voltage supply node coupled to a first electrode of the upper transistor and a second voltage supply node is coupled to a second electrode of the lower transistor. An upper driver transistor selectively couples a gate electrode of the upper transistor to an upper drive voltage node, the upper driver transistor having a control electrode coupled to an upper switched voltage supply circuit.

Abstract: A method and apparatus for direct conversion of digital data to high power RF signals, known as DDRF. The method and apparatus receive a digital signal, create a digital modulated signal therefrom, and amplify the modulated signal with an H-bridge Power Amplifier for transmission. DDRF uses a multi-level H-bridge amplification circuit to establish a more power efficient digital transmitter.

Abstract: An H-bridge circuit formed from two sub-circuits coupled to each other by a load network across a respective load node of each of the sub-circuits. Each sub-circuit of the two sub-circuits comprises a depletion mode upper transistor with a second electrode coupled to a first electrode of a lower transistor. The load node of the sub-circuit is disposed between the second electrode of the upper transistor and the first electrode of a lower transistor. There is a first voltage supply node coupled to a first electrode of the upper transistor and a second voltage supply node is coupled to a second electrode of the lower transistor. An upper driver transistor selectively couples a gate electrode of the upper transistor to an upper drive voltage node, the upper driver transistor having a control electrode coupled to an upper switched voltage supply circuit.

Abstract: A method and apparatus for direct conversion of digital data to high power RF signals, known as DDRF. The method and apparatus receive a digital signal, create a digital modulated signal therefrom, and amplify the modulated signal with an H-bridge Power Amplifier for transmission. DDRF uses a multi-level H-bridge amplification circuit to establish a more power efficient digital transmitter.

Abstract: A method and system for creating a spectral null in a switching amplifier system is provided. The method includes receiving an input signal in a first modulated form at an input stage 104 of the amplifier. The method further includes converting the input signal to a second modulated form. The input signal in the second modulated form is referred to as a first switching signal. Further, the method includes determining switching frequency of the first switching signal from a predefined cycle time of the first switching signal. Thereafter, the method includes inverting the first switching signal and delaying it by a predefined delay amount. The inverted and delayed first switching signal is referred to as a second switching signal The method further includes summing the first switching signal from the second switching signal, which results in a two-state output signal. The two-state output signal is free of any components at the switching frequency and its odd harmonics.

Abstract: A method and apparatus for predistortion training in an amplifier using predistortion is provided herein. Predistortion takes place by collecting a series of envelope errors and averaging the envelope errors for various amplitude regions. LUT values are modified based on a curve-fit to the average amplitude values for each amplitude region. By utilizing a curve-fitting technique, the pitfalls of modifying individual LUT coefficients is avoided. Particularly, because the errors are collected in relatively broad regions and then averaged, the importance of exact correlation between a measured error and a specific LUT entry is significantly lessened.