Patents by Inventor Curtis Matheson Webster

Curtis Matheson Webster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for gate training in a memory system
    Patent number: 8422319
    Abstract: A system and method for gate training in a memory system is disclosed. In one embodiment, in a method for calibrating read data strobe gating, a first read command is issued to a memory module. A first DQS gate signal is issued before the beginning of the preamble of a first DQS signal received from the memory module that corresponds to the first read command. A second read command is issued to the memory module such that the preamble of a second DQS signal received from the memory module that corresponds to the second read command is adjacent to the postamble of the first DQS signal. Then, a second DQS gate signal is issued at a preset time after the first DQS gate signal. The second DQS signal is sampled repeatedly to locate the preamble of the second DQS signal.
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: April 16, 2013
    Assignee: LSI Corporation
    Inventors: Srinivas Sriadibhatla, Curtis Matheson Webster
  • SYSTEM AND METHOD FOR GATE TRAINING IN A MEMORY SYSTEM
    Publication number: 20120307577
    Abstract: A system and method for gate training in a memory system is disclosed. In one embodiment, in a method for calibrating read data strobe gating, a first read command is issued to a memory module. A first DQS gate signal is issued before the beginning of the preamble of a first DQS signal received from the memory module that corresponds to the first read command. A second read command is issued to the memory module such that the preamble of a second DQS signal received from the memory module that corresponds to the second read command is adjacent to the postamble of the first DQS signal. Then, a second DQS gate signal is issued at a preset time after the first DQS gate signal. The second DQS signal is sampled repeatedly to locate the preamble of the second DQS signal.
    Type: Application
    Filed: May 30, 2011
    Publication date: December 6, 2012
    Inventors: SRINIVAS SRIADIBHATLA, Curtis Matheson Webster