Abstract: An integrated circuit test system. The test system includes a controller and an integrated circuit coupled to a voltage source and a current monitor. The controller causes the voltage source to supply a voltage to the integrated circuit, receives a signal from the current monitor indicating a power dissipation of the integrated circuit, and causes the voltage source to reduce the voltage until the signal from the current monitor indicates the power dissipation of the integrated circuit is less than a predetermined threshold. The controller stores in the integrated circuit in a non-volatile storage register that is accessible via a subset of access pins, a value corresponding to the voltage supplied to the integrated circuit when the power dissipation of the integrated circuit is less than the predetermined threshold. The subset of access pins provides at least one function in addition to accessing the non-volatile storage register.

Abstract: A system is provided for detecting when a temperature of a multiprocessor chip approaches an established threshold temperature indicating an imminent overheat condition. When the threshold temperature is reached, a number of active threads are idled in order to remove their contribution from the overall power consumption of the multiprocessor chip. Idling of the threads serves to prevent the multiprocessor chip from reaching the overheat condition. Once the temperature of the multiprocessor chip drops to an acceptable level, execution of the previously idled threads is resumed. Detection of the imminent overheat condition and corresponding idling of the threads to avoid reaching the overheat condition is conducted by hardware to ensure timely reduction of the multiprocessor chip temperature.

Abstract: A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each of the data chunks including at least an error correction code portion and a data portion; and a first chunk of said plurality of data chunks having a tag portion, wherein said tag portion includes tag information for the entire line of memory, and wherein subsequent ones of said data chunks do not include tag information.

Abstract: Embodiments of the present invention include a memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent. The memory controller includes at least one memory-controller agent, an incoming memory-transaction dispatch unit, and an outgoing memory-transaction completion unit. Each memory-controller agent has a memory-line memory controller and a memory-line coherency controller, along with a cache memory capable of caching the contents of a memory line along with coherency information for the memory line. Memory transactions are received from cacheable entities of a computer system at the incoming memory-transaction dispatch unit, and are then presented to one or more agents. If multiple memory-read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests.

Abstract: A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is implemented in a networked multiprocessor computing system, and includes, in each coherency controller of each of the memories in the system, a mechanism to reserve at least one slot of the memory access request transaction queue for exclusive processing of processor return (PR) transactions to provide an uninterrupted processing of PR transactions. The number of blocking (BL) transaction is limited to a number less than available slots. The distributed shared memory system also includes a distributed memory return transaction queue that allows each of entries in the memory access request transaction queue to add a plurality of memory return transactions per clock cycle.

Abstract: A directory tag for each cache line in a memory within a multiprocessor distributed memory system includes a share mask and an alias signature. The share mask is used to keep track of entities of the system that share the cache line, and is encoded into a fixed length field having a number of bits that is significantly less than the number of the entities. The share mask is utilized for maintaining coherency among shared data in the system. Before a request to access a location of a memory is granted, the share mask is used to identify each entity or a group of entities that share the particular location, and an invalidate message is sent to each of the identified entity or group of entities. The alias signature in the directory tag is compared with an alias signature computed from the memory access request to prevent data corruptions that may occur due to incorrect memory aliasing.

Abstract: A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is implemented in a networked multiprocessor computing system, and includes, in each coherency controller of each of the memories in the system, a mechanism to reserve at least one slot of the memory access request transaction queue for exclusive processing of processor return (PR) transactions to provide an uninterrupted processing of PR transactions. The number of blocking (BL) transaction is limited to a number less than available slots. The distributed shared memory system also includes a distributed memory return transaction queue that allows each of entries in the memory access request transaction queue to add a plurality of memory return transactions per clock cycle.

Abstract: A directory tag for each cache line in a memory within a multiprocessor distributed memory system includes a share mask and an alias signature. The share mask is used to keep track of entities of the system that share the cache line, and is encoded into a fixed length field having a number of bits that is significantly less than the number of the entities. The share mask is utilized for maintaining coherency among shared data in the system. Before a request to access a location of a memory is granted, the share mask is used to identify each entity or a group of entities that share the particular location, and an invalidate message is sent to each of the identified entity or group of entities, eliminating the need to broadcast the message to all entities in the system, and thus conserving the communication bandwidth of the system.

Abstract: A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is implemented in a networked multiprocessor computing system, and includes, in each coherency controller of each of the memories in the system, a mechanism to reserve at least one slot of the memory access request transaction queue for exclusive processing of processor return (PR) transactions to provide an uninterrupted processing of PR transactions. The number of blocking (BL) transaction is limited to a number less than available slots. The distributed shared memory system also includes a distributed memory return transaction queue that allows each of entries in the memory access request transaction queue to add a plurality of memory return transactions per clock cycle.

Abstract: A memory controller provides memory line caching and memory transaction coherency by using at least one memory controller agent. A memory controller in accordance with the present invention includes at least one memory controller agent, an incoming memory transaction dispatch unit, and an outgoing memory transaction completion unit. Each memory controller agent has a memory line memory controller and a memory line coherency controller, along with a cache memory capable of caching the contents of a memory line along with coherency information for the memory line. Memory transactions are received from cacheable entities of a computer system at the incoming memory transaction dispatch unit, and are then presented to one or more agents. For each incoming transaction, one of the agents will accept the transaction. If multiple memory read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests.

Abstract: A directory tag for each cache line in a memory within a multiprocessor distributed memory system includes a share mask and an alias signature. The share mask is used to keep track of entities of the system that share the cache line, and is encoded into a fixed length field having a number of bits that is significantly less than the number of the entities. The share mask is utilized for maintaining coherency among shared data in the system. Before a request to access a location of a memory is granted, the share mask is used to identify each entity or a group of entities that share the particular location, and an invalidate message is sent to each of the identified entity or group of entities, eliminating the need to broadcast the message to all entities in the system, and thus conserving the communication bandwidth of the system.

Abstract: A hardware-based linked list queues memory transactions in a memory controller. The memory controller includes a plurality of memory controller agents. Each agent has a head flag, a tail flag, and a next agent field, thereby allowing the agents to be arranged into linked lists. Memory transactions are received from cacheable entities of a computer system at an incoming memory transaction dispatch unit via an interconnection fabric. The incoming transactions are then presented to the plurality of agents. For each incoming read transaction, one of the agents will accept the transaction. If there are pending memory read transactions for the memory line, then the accepting agent joins a linked list of agents that are queued up to access that memory line. The accepting agent drives its index out onto a bus that connects all agents. One agent in the linked list will have its tail flag set, and that agent will clear its tail flag and latch into its next agent field the index provided by the accepting agent.

Abstract: A memory controller has separate memory controller agents that process memory transactions in parallel. A memory controller in accordance with the present invention includes a plurality of memory controller agents, which are coupled to each other via a series of busses, an incoming memory transaction dispatch unit, and an outgoing memory dispatch unit. Memory transactions are received from cacheable entities of a computer system at the incoming memory transaction dispatch unit, and are then presented to the plurality of agents. For each incoming transaction, one of the agents will accept the transaction. Each agent is responsible for ensuring coherency and fulfilling memory transactions for a single memory line. If multiple memory read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests.

Abstract: An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.

Abstract: A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each of the data chunks including at least an error correction code portion and a data portion; and a first chunk of said plurality of data chunks having a tag portion, wherein said tag portion includes tag information for the entire line of memory, and wherein subsequent ones of said data chunks do not include tag information.

Abstract: A memory system includes a main memory controller supplying data in response to transactions received by the main memory controller. A plurality of modules each include a cache memory for storing data supplied by the main memory controller. The modules request data from the main memory controller by sending module generated transactions to the main memory controller. A cache tag array includes a cache tag corresponding to each data line stored in memory, there being a one-to-one correspondence between the cache tags and the data lines. The data lines together with their associated cache tags are combined and arranged in a plurality of sequential data chunks, the cache tags included in an initial portion of the data chunks (i.e, a first sequence of bits) followed by inclusion of the data lines in a subsequent portion of the data chunks (i.e., the usable bit positions following inclusion of all of the cache tag bits.) Each of the chunks may further include appropriate ECC bits.

Abstract: An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.

Abstract: A memory controller and method for intermittently providing a clock signal to a synchronous memory. While no transactions are occurring, a clock signal is held in an idle state. Upon the start of a transaction with the synchronous memory, the clock signal is activated. When activated, the clock signal functions as a periodic timing reference clock. The clock signal remains active during the transaction. Upon completion of the transaction, the clock signal returns to the idle state. In one embodiment, a finite state machine utilizes a counter to control the process. Upon the start of a transaction with the synchronous memory a new count is loaded in a counter. The value for the new count depends, for example, on the number of commands necessary to complete the transaction. The counter, beginning with the new count, regularly increments. When the counter reaches a maximum value, the clock signal returns to the idle state.

Abstract: The present invention relates to an intelligent direct memory access (DMA) controller which interprets user commands from a host system, establishes work buffers for each user process, and retrieves blocks of data from the work buffers at the user's is request, rather than at the request of the kernel software. This is accomplished by establishing work buffers for each user process which are locked into physical memory. The controlling user process will then fill one work buffer, acquire the device semaphore, start physical DMA on the locked buffer, and then start filling another buffer. Memory integrity is maintained by allowing the user to access the work buffers for DMA without knowing their physical location in memory, via work buffer pointers from work buffer pointer registers which correspond to each work buffer for each user process. These work buffer pointer registers are privileged and are updated by the host processor for each new controlling user process.