Abstract: A method and apparatus in a data processing system for multiple bus arbitration, wherein the data processing system includes a first bus connected to a second bus by a bridge. In response to receiving a request for a target device from a master device connected to a first bus, a determination is made as to whether the target device is connected to the first bus. The bridge is selected in response to determining that the target device is located on the second bus. The bridge initiates a request for the second bus in response to the selection of the bridge. The first bus and the second bus are connected to each other by the bridge in response to the bridge receiving a grant to the second bus, wherein the master device transfers data between the master device and the target device across the bridge.

Abstract: Reusable tags are assigned to read and write requests on a tagged access synchronous bus. This allows multiple reads to be queued and overlapped on the tagged access synchronous bus to maximize data transfer rates. Writes are buffered to similarly allow multiple writes to be over-lapped. All data transfers on the tagged access synchronous bus typically would default to a cache block amount of data, with critical word first and early termination capabilities provided to permit processor execution to proceed without waiting for an entire cache block to be loaded. The tagged access synchronous bus architecture thus allows the system to take full advantage of high speed memory devices such as SDRAMs, RDRAMs, etc. while decoupling the bus data transfers from processor execution for increased overall system performance.