Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may heat them when their temperatures fall outside of thermal operating ranges. To heat the hardware components, the data processing system may implement a dual device detection framework to identify and characterize various devices that may be usable to heat its hardware components.

Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may heat them when their temperatures fall outside of thermal operating ranges. To mitigate some risk associated with heating, the data processing system may proactively validate the operation of hardware and/or software used to manage the components that provide the heat.

Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may heat them when their temperatures fall outside of thermal operating ranges. The data processing system may implement a distributed management framework for managing the operation of a thermal management subsystem tasked with maintaining the temperatures of the hardware components through heating.

Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may implement a framework for improving the likelihood that the management components have access to consistent state information. The framework may include use of multiple management components that conserve and/or distribute information regarding the states of and events impacting the operation of hardware components.

Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may heat them when their temperatures fall outside of thermal operating ranges. To mitigate some risk associated with heating, the data processing system may proactively calibrate temperature sensors used to guide the heating process.

Abstract: An information handling system (IHS), peripheral component interface (PCI) system and method for expanding PCI nodes in an IHS. The PCI system includes a primary PCI node. The primary PCI node has a PCI switch communicatively coupled to a processor via a system interconnect. The PCI switch is communicatively coupled to several PCI devices. A communication module is communicatively coupled to the PCI switch. A PCI expansion node is communicatively coupled to the primary PCI node via a PCI bus and a sideband bus. The IHS executes firmware that enables expansion of the IHS by configuring the primary PCI node to recognize the one or more interconnected PCI expansion nodes and integrate the functions of the interconnected PCI expansion nodes into an expanded PCI subsystem. The primary PCI node and PCI expansion node can be substantially identical IHSs, having the same motherboards and chassis.

Abstract: An information handling system (IHS), peripheral component interface (PCI) system and method for expanding PCI nodes in an IHS. The PCI system includes a primary PCI node. The primary PCI node has a PCI switch communicatively coupled to a processor via a system interconnect. The PCI switch is communicatively coupled to several PCI devices. A communication module is communicatively coupled to the PCI switch. A PCI expansion node is communicatively coupled to the primary PCI node via a PCI bus and a sideband bus. The IHS executes firmware that enables expansion of the IHS by configuring the primary PCI node to recognize the one or more interconnected PCI expansion nodes and integrate the functions of the interconnected PCI expansion nodes into an expanded PCI subsystem. The primary PCI node and PCI expansion node can be substantially identical IHSs, having the same motherboards and chassis.

Abstract: A port securing module includes a power gate that is operable to be coupled in series to a power source and to a load. A resistor is coupled in parallel to the power gate. An operational amplifier includes an inverting input and a non-inverting input that couple the operational amplifier in parallel to each of the power gate and the resistor. The operational amplifier also includes an output that is operable to indicate whether a load is coupled to the power gate and, if a load is coupled to the power gate, supply a voltage to activate the power gate such that power is supplied to the load.

Abstract: A port securing module includes a power gate that is operable to be coupled in series to a power source and to a load. A resistor is coupled in parallel to the power gate. An operational amplifier includes an inverting input and a non-inverting input that couple the operational amplifier in parallel to each of the power gate and the resistor. The operational amplifier also includes an output that is operable to indicate whether a load is coupled to the power gate and, if a load is coupled to the power gate, supply a voltage to activate the power gate such that power is supplied to the load.

Abstract: A port securing module includes a power gate that is operable to be coupled in series to a power source and to a load. A resistor is coupled in parallel to the power gate. An operational amplifier includes an inverting input and a non-inverting input that couple the operational amplifier in parallel to each of the power gate and the resistor. The operational amplifier also includes an output that is operable to indicate whether a load is coupled to the power gate and, if a load is coupled to the power gate, supply a voltage to activate the power gate such that power is supplied to the load.

Abstract: A port securing module includes a power gate that is operable to be coupled in series to a power source and to a load. A resistor is coupled in parallel to the power gate. An operational amplifier includes an inverting input and a non-inverting input that couple the operational amplifier in parallel to each of the power gate and the resistor. The operational amplifier also includes an output that is operable to indicate whether a load is coupled to the power gate and, if a load is coupled to the power gate, supply a voltage to activate the power gate such that power is supplied to the load.

Abstract: Polling of devices on an inter-IC (I.sup.2 C) is provided. An expansion processor resides on a primary I.sup.2 C bus. The expansion processor is coupled to a plurality of I.sup.2 C sub-buses each of which may host a plurality of I.sup.2 C devices. Data is transferred between the expansion processor and the plurality of I.sup.2 C devices via the corresponding sub-bus according to an I.sup.2 C protocol. Data transfer is in response to a request initiated by a bus master on the primary I.sup.2 C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which then echos it to the target device.