Abstract: A differential amplifier for providing common-mode rejection while providing differential-mode amplification includes an active differential amplification element electrically coupled to a first input signal, a second input signal and an output signal. The active differential amplification element is also electrically coupled to a first voltage and to a different second voltage. A passive bias element is electrically coupled to the active differential amplification element. The passive bias element is capable of biasing the active differential amplification element so that the active differential amplification element operates in a saturation mode. The active differential amplification element thereby generates the output signal so that the output signal corresponds to a voltage difference between the first input signal and the second input signal.

Abstract: Methods and apparatus are provided for implementing a receiver capable of receiving signals in simultaneous bi-directional current mode differential links. The receiver comprises a resistor-summing network and a differential amplifier. The resistor-summing network can also comprise capacitors for the purpose of attenuating high-frequency noise at the differential amplifier. The high-frequency noise can arise from impedance discontinuities in the signal paths or from differences in rising or falling transition times between the data driver and the replica driver in the links.

Abstract: Measurement of the period of a relatively slow but precise reference clock in terms of a high speed oscillating clock, such as from a voltage controlled oscillator (VCO). The reference clock is known to be accurate and stable and values of the time measurement unit are output that determine the integer and fractional number of the high speed oscillating clock periods which occurred during one reference clock cycle. The measurements are very accurate and all cycles of the reference clock are measured. Such measurements enable various frequency control schemes over the high speed oscillating clock source.

Abstract: A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A differential receiver-amplifier having reduced input distortion at differential input (positive and negative) terminals to the differential receiver-amplifier. The output from the differential receiver-amplifier is generated from a differential signal detector receiving each differential input from one of a pair of differential amplifiers.

Abstract: A differential receiver-amplifier having reduced input distortion at differential input (positive and negative) terminals to the differential receiver-amplifier. The output from the differential receiver-amplifier is generated from a differential signal detector receiving each differential input from one of a pair of differential amplifiers.

Abstract: A feedback mechanism is provided to a current mode differential driver by connecting the center tap of a terminator of the output of the driver through feedback resistors to the gates of a positive and a negative current source connected to the driver. Connecting the center tap between the feedback resistors, the average common mode voltage at the output of the differential driver is substantially constant which avoids variations and reflective noise in high speed data transmission that can occur because of manufacturing tolerances.

Abstract: Methods and apparatus are provided for implementing a receiver capable of receiving signals in simultaneous bi-directional current mode differential links. The receiver comprises a resistor-summing network and a differential amplifier. The resistor-summing network can also comprise capacitors for the purpose of attenuating high-frequency noise at the differential amplifier. The high-frequency noise can arise from impedance discontinuities in the signal paths or from differences in rising or falling transition times between the data driver and the replica driver in the links.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A differential amplifier for providing common-mode rejection while providing differential-mode amplification includes an active differential amplification element electrically coupled to a first input signal, a second input signal and an output signal. The active differential amplification element is also electrically coupled to a first voltage and to a different second voltage. A passive bias element is electrically coupled to the active differential amplification element. The passive bias element is capable of biasing the active differential amplification element so that the active differential amplification element operates in a saturation mode. The active differential amplification element thereby generates the output signal so that the output signal corresponds to a voltage difference between the first input signal and the second input signal.

Abstract: A high speed voltage level shifter and phase splitter circuit is provided. The voltage level shifter and phase splitter circuit includes an input signal and a first input inverter stage that receives the input signal and provides an inverted delayed out of phase signal to the input signal. A buffer stage receives the input signal and provides a buffered delayed in phase signal to the input signal. A first constant current source is coupled between the first input inverter stage and the buffer stage. A first output inverter stage is coupled to the first constant current source and provides a voltage level shifted and out of phase signal to the input signal. A second constant current source is coupled between the first input inverter stage and the buffer stage having an opposite polarity as the first constant current source. A second output inverter stage is coupled to the second constant current source and providing a voltage level shifted and in phase signal to the input signal.

Abstract: An echo cancellation circuit for neutralizing signal reflections in a differential link interface, and a method for achieving the same. The differential link interface includes a line driver that generates a line drive signal and a replica driver for generating a replica signal that mirrors the line drive signal within the differential link. The echo cancellation circuit includes a slope adjustment device within the replica driver for temporarily altering the slope of the replica line drive signal during a signal reflection at the output of the line driver, such that the amplitude of the replica signal corresponds to the amplitude of the line drive signal during the signal reflection.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) current mode differential link with precompensation is provided. The Complementary Metal Oxide Semiconductor (CMOS) bi-directional current mode differential link with precompensation includes a CMOS driver receiving a data input and having an output coupled to a transmission line. A CMOS replica driver receives the data input and provides a replica driver output substantially equal to the CMOS driver output. A CMOS receiver is coupled to both the transmission line and replica driver output. The CMOS receiver subtracts the replica driver output from a signal at the transmission line. The CMOS driver and the CMOS replica driver include a plurality of parallel current sources. Each of the current sources is arranged to send positive or negative current through a load responsive to an applied control signal. The use of the plurality of parallel current sources allows the CMOS driver to effectively implement precompensation.

Abstract: A control system for minimizing and controlling the current slew rate of an output device by using inductance to directly measure the current slew rate is provided. The control system may, for example, be used to control and minimize the current slew rate through signal drivers and allow for faster drivers and/or larger numbers of drivers on integrated circuit chips. In accordance with one embodiment of the invention, an inductor is serially coupled with an output device. A predriver is coupled to the gate of the output device for providing a voltage slew rate at the output device gate. A comparator is coupled to the inductor for sensing a voltage indicative of a current slew rate through the inductor and outputing a signal indicating whether the current slew rate exceeds or falls below a desired level.

Abstract: A digital data waveform precompensated for off-chip cable attenuation includes peaks with exponential tails at signal transitions. A driver output stage generating the waveform includes an output transistor pulling the output to a peak voltage level when an input goes high. After a delay, a transistor closes a feedback loop containing a resistive load, exponentially changing the voltage level of the output to a final voltage level. A complementary output transistor pulls the output to a ground voltage level when the input goes low, with a transistor closing a feedback loop containing a resistive load for exponential change of the output to a final voltage level. The separate resistive paths equalize the time constant of the exponential tails despite a difference in the gate capacitances of the output transistors. The received waveform after cable attenuation exhibits pulse shapes closer to the predefined pulse shapes on which a receiver is designed to operate.

Abstract: A method and apparatus that can test self-timed parallel interfaces operating at system speed. An output stage is provided for queuing a test packet and providing the test packet to an input stage. The packet contains a data bit stream and error detection code such as cyclic redundancy check code. The input stage is coupled to the output stage and receives the test packet to determine the correctness of the data bit stream. On the input stage, the error detection code verifier recalculates the error detection code and compares the recalculated error detection code with the error detection code attached to the data bit stream to determine the correctness of the data bit steam. The output queue has a first input port for receiving data from drivers on the interface and a second input port for receiving a pseudo random data bit stream. A pseudo random data generator generates a pseudo random data bit stream. The data bit stream may be packetized according to a predetermined protocol.

Abstract: A full-duplex, differential, bi-directional communications link for simultaneously transmitting differential data between electronic devices is provided. Each transceiver coupled to the communications channel comprises a CMOS (Complementary Metal-Oxide Semiconductor) differential driver and receiver. The differential driver provides constant CMOS voltage sources for providing stable data signal transmission at reduced voltage levels. Voltage sources providing a data signal voltage different from the desired data signal voltage can be placed into a high impedance mode to allow the desired data signal voltage to be transmitted on the common line. The differential receiver includes self-biasing feedback circuitry to provide biasing voltages to the circuit while avoiding manufacturing difficulties associated with providing precise bias voltages. The complementary amplifier structure of the receiver provides an increased common mode noise tolerance.