Patents by Inventor Curtis Ward
Curtis Ward has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12080639Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.Type: GrantFiled: September 23, 2019Date of Patent: September 3, 2024Assignee: Intel CorporationInventors: Rami Hourani, Manish Chandhok, Richard E. Schenker, Florian Gstrein, Leonard P. Guler, Charles H. Wallace, Paul A. Nyhus, Curtis Ward, Mohit K. Haran, Reken Patel
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Patent number: 11972979Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.Type: GrantFiled: June 7, 2023Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Leonard P. Guler, Michael Harper, Suzanne S. Rich, Charles H. Wallace, Curtis Ward, Richard E. Schenker, Paul Nyhus, Mohit K. Haran, Reken Patel, Swaminathan Sivakumar
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Patent number: 11881520Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.Type: GrantFiled: December 29, 2017Date of Patent: January 23, 2024Assignee: Intel CorporationInventors: Curtis Ward, Heidi M. Meyer, Michael L. Hattendorf, Christopher P. Auth
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Publication number: 20230326794Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.Type: ApplicationFiled: June 7, 2023Publication date: October 12, 2023Inventors: Leonard P. GULER, Michael HARPER, Suzanne S. RICH, Charles H. WALLACE, Curtis WARD, Richard E. SCHENKER, Paul NYHUS, Mohit K. HARAN, Reken PATEL, Swaminathan SIVAKUMAR
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Patent number: 11721580Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.Type: GrantFiled: June 10, 2019Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Leonard P. Guler, Michael Harper, Suzanne S. Rich, Charles H. Wallace, Curtis Ward, Richard E. Schenker, Paul Nyhus, Mohit K. Haran, Reken Patel, Swaminathan Sivakumar
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Publication number: 20230207664Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Inventors: Michael L. HATTENDORF, Curtis WARD, Heidi M. MEYER, Tahir GHANI, Christopher P. AUTH
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Patent number: 11640985Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.Type: GrantFiled: January 15, 2021Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Michael L. Hattendorf, Curtis Ward, Heidi M. Meyer, Tahir Ghani, Christopher P. Auth
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Publication number: 20230126174Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.Type: ApplicationFiled: December 23, 2022Publication date: April 27, 2023Inventors: Curtis WARD, Heidi M. MEYER, Michael L. HATTENDORF, Christopher P. AUTH
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Publication number: 20210143051Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.Type: ApplicationFiled: January 15, 2021Publication date: May 13, 2021Inventors: Michael L. HATTENDORF, Curtis WARD, Heidi M. MEYER, Tahir GHANI, Christopher P. AUTH
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Publication number: 20210090990Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Rami HOURANI, Manish CHANDHOK, Richard E. SCHENKER, Florian GSTREIN, Leonard P. GULER, Charles H. WALLACE, Paul A. NYHUS, Curtis WARD, Mohit K. HARAN, Reken PATEL
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Patent number: 10930753Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.Type: GrantFiled: December 29, 2017Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Michael L. Hattendorf, Curtis Ward, Heidi M. Meyer, Tahir Ghani, Christopher P. Auth
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Publication number: 20200388534Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.Type: ApplicationFiled: June 10, 2019Publication date: December 10, 2020Inventors: Leonard P. GULER, Michael HARPER, Suzanne S. RICH, Charles H. WALLACE, Curtis WARD, Richard E. SCHENKER, Paul NYHUS, Mohit K. HARAN, Reken PATEL, Swaminathan SIVAKUMAR
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Publication number: 20200227413Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction.Type: ApplicationFiled: December 29, 2017Publication date: July 16, 2020Inventors: Curtis WARD, Heidi M. MEYER, Michael L. HATTENDORF, Christopher P. AUTH
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Publication number: 20190164808Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.Type: ApplicationFiled: December 29, 2017Publication date: May 30, 2019Inventors: Michael L. HATTENDORF, Curtis WARD, Heidi M. MEYER, Tahir GHANI, Christopher P. AUTH
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Patent number: 9630663Abstract: A track system for use with multiple in-line wheels of a vehicle is disclosed. The track includes a plurality of track members linked together forming a loop encircling the wheels. The track members each include a base, sidewalls, and a removable shoe. The shoe can be bolted to the base and can be removed from the base. The shoe can have a rubber pad, a grouser, or another tread.Type: GrantFiled: January 18, 2011Date of Patent: April 25, 2017Assignee: Ward Equipment, LLCInventor: Curtis Ward
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Publication number: 20050148180Abstract: The present invention relates to exposing a bond pad on a substrate. A bond pad is formed over a silicon substrate with the subsequent formation of a dielectric over the bond pad. A patterned resist is formed, and at least opening is processed to form a sloped sidewall profile. The sloped sidewall profile is subsequently etched and transferred to the dielectric layer, exposing the bond pad.Type: ApplicationFiled: December 30, 2003Publication date: July 7, 2005Inventors: Swaminathan Sivakumar, Curtis Ward, Timothy Hehr, Mark Fradkin
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Publication number: 20040265748Abstract: A method of forming a device feature using an extreme ultraviolet (EUV) imaging layer (or a sub-deep ultraviolet imaging layer) and one or more other masks layers. The method includes forming a device feature layer; forming a photoresist layer over the device feature layer; forming a contact mask layer (CML) over the photoresist layer; forming an extreme ultraviolet (EUV) imaging layer over the CML; forming a first opening through the EUV imaging layer to expose a first underlying region of the CML; forming a second opening through the CML to expose a second underlying region of the photoresist layer, wherein the second opening is situated directly below the first opening; forming a third opening through the photoresist layer to expose a third underlying region of the device feature layer, wherein the third opening is situated directly below the second opening; forming a fourth opening through the device feature material layer, wherein the fourth opening is situated directly below the third opening.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventors: Robert Bristol, Heidi Cao, Robert Meagley, Bryan Rice, Curtis Ward