Patents by Inventor Cynthia Allison

Cynthia Allison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10489875
    Abstract: One embodiment of the present invention includes a method for tracking which cache tiles included in a plurality of cache tiles are intersected by a plurality of bounding boxes. The method includes receiving the plurality of bounding boxes, wherein each bounding box is associated with one or more graphics primitives being rendered to a render surface, and wherein the render surface is divided into the plurality of cache tiles. The method further includes, for each bounding box included in the plurality of bounding boxes, determining one or more cache tiles included in the plurality of cache tiles that are intersected by the bounding box, and storing a result in an array for each cache tile that is intersected by the bounding box. Finally, the method includes determining not to process a cache tile included in the plurality of cache tiles based on the results stored in the array.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 26, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad S. Hakura, Cynthia Allison
  • Patent number: 10430989
    Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 1, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad Hakura, Cynthia Allison, Dale Kirkland, Jeffrey Bolz, Yury Uralsky, Jonah Alben
  • Patent number: 10147222
    Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 4, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad Hakura, Cynthia Allison, Dale Kirkland, Jeffrey Bolz, Yury Uralsky, Jonah Alben
  • Publication number: 20170148204
    Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 25, 2017
    Inventors: Ziyad HAKURA, Cynthia ALLISON, Dale KIRKLAND, Jeffrey BOLZ, Yury URALSKY, Jonah ALBEN
  • Publication number: 20170148203
    Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 25, 2017
    Inventors: Ziyad HAKURA, Cynthia ALLISON, Dale KIRKLAND, Jeffrey BOLZ, Yury URALSKY, Jonah ALBEN
  • Patent number: 9342311
    Abstract: One embodiment of the present invention includes a method for generating accumulated bounding boxes for graphics primitives. The method includes generating a first bounding box associated with a first graphics primitive. The method further includes, for each graphics primitive included in a first set of one or more additional graphics primitives, determining that the graphics primitive is within a threshold distance of the first bounding box, and adding the graphics primitive to the first bounding box. The method further includes determining not to add a second graphics primitive to the first bounding box. The method further includes generating a second bounding box associated with the second graphics primitive. Finally, the method includes transmitting the first bounding box to a tiling unit via a crossbar. One advantage of the disclosed embodiments is that multiple bounding boxes are combined to generate an accumulated bounding box that is then transferred across the crossbar.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: May 17, 2016
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Pierre Souillot, Cynthia Allison, Dale L. Kirkland, Rouslan Dimitrov
  • Patent number: 9336002
    Abstract: One embodiment of the present invention includes a method for performing a multi-pass tiling test. The method includes combining a plurality of bounding boxes to generate a coarse bounding box. The method further includes identifying a first cache tile associated with a render surface and determining that the coarse bounding box intersects the first cache tile. The method further includes comparing each bounding box included in the plurality of bounding boxes against the first cache tile to determine that a first set of one or more bounding boxes included in the plurality of bounding boxes intersects the first cache tile. Finally, the method includes, for each bounding box included in the first set of one or more bounding boxes, processing one or more graphics primitives associated with the bounding box. One advantage of the disclosed technique is that the number of intersection calculations performed for each cache tile is reduced.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: May 10, 2016
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Pierre Souillot, Cynthia Allison, Dale L. Kirkland
  • Publication number: 20140118381
    Abstract: One embodiment of the present invention includes approaches for processing graphics primitives associated with cache tiles when rendering an image. A set of graphics primitives associated with a first render target configuration is received from a first portion of a graphics processing pipeline, and the set of graphics primitives is stored in a memory. A condition is detected indicating that the set of graphics primitives is ready for processing, and a cache tile is selected that intersects at least one graphics primitive in the set of graphics primitives. At least one graphics primitive in the set of graphics primitives that intersects the cache tile is transmitted to a second portion of the graphics processing pipeline for processing. One advantage of the disclosed embodiments is that graphics primitives and associated data are more likely to remain stored on-chip during cache tile rendering, thereby reducing power consumption and improving rendering performance.
    Type: Application
    Filed: September 10, 2013
    Publication date: May 1, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ziyad S. HAKURA, Robert OHANNESSIAN, Cynthia ALLISON, Dale L. KIRKLAND
  • Patent number: 8704826
    Abstract: One embodiment of the present invention includes approaches for processing graphics primitives associated with cache tiles when rendering an image. A set of graphics primitives associated with a first render target configuration is received from a first portion of a graphics processing pipeline, and the set of graphics primitives is stored in a memory. A condition is detected indicating that the set of graphics primitives is ready for processing, and a cache tile is selected that intersects at least one graphics primitive in the set of graphics primitives. At least one graphics primitive in the set of graphics primitives that intersects the cache tile is transmitted to a second portion of the graphics processing pipeline for processing. One advantage of the disclosed embodiments is that graphics primitives and associated data are more likely to remain stored on-chip during cache tile rendering, thereby reducing power consumption and improving rendering performance.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: April 22, 2014
    Assignee: Nvidia Corporation
    Inventors: Ziyad S. Hakura, Robert Ohannessian, Cynthia Allison, Dale L. Kirkland
  • Publication number: 20060219130
    Abstract: The present invention relates to the use of esterified tall oil rosin, esterified wood rosin, esterified gum rosin, and mixtures thereof to enhance water-based flexographic ink. The products and methods of the present invention result in enhanced image clarity and resolution; enhanced image clarity and resolution as a result of elimination of most press-side imperfections such as ghosting, inefficient ink transfer and bronzing; increased ink mileage up to three times that of conventional water-based inks; achievement of fine-line details; increased gloss properties on high hold-out liners; and increased color strength and density on most paper and paperboard substrates.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 5, 2006
    Inventors: Cynthia Allison, Barry Williams