Abstract: The present invention provides an integrated circuit and method of manufacture therefore. The integrated circuit, in one embodiment, includes heat conducting elements located proximate a plurality of heat generating components located over a substrate. The integrated circuit may further include a heat radiating element comprising one or more fins in thermal communication and physical contact with the heat conducting elements, the heat radiating element configured to dissipate heat generated by the heat generating components away from the integrated circuit.

Abstract: Methods and apparatus are provided for designing a logic circuit using one or more circuit elements having a substantially continuous range of values. A circuit is designed based on a functional description of the circuit and one or more circuit constraints. The circuit is initially designed using a library of discrete circuit element options. The initial circuit design is evaluated to determine whether one or more discrete circuit elements cause the circuit to not satisfy the one or more circuit constraints, such as power, area or timing requirements for the circuit. At least one replacement circuit element is generated that has at least one cell parameter configured such that the at least one replacement circuit element will have a performance characteristic that allows the circuit to satisfy the one or more circuit constraints.

Abstract: A method for nondestructively characterizing alignment overlay between two layers of a semiconductor wafer. An incident beam of radiation is directed upon the wafer surface and the properties of the resulting diffracted beam are determined, in one embodiment as a function of wavelength or incident angle. The spectrally or angularly resolved characteristics of the diffracted beam are related to the alignment of the overlay features. A library of calculated diffraction spectra is established by modeling a full range of expected variations in overlay alignment. The spectra resulting from the inspection of an actual wafer having alignment targets in at least two layers is compared against the library to identify a best fit to characterize the actual alignment. The results of the comparison may be used as an input for upstream and/or downstream process control.

Abstract: A method for nondestructively characterizing alignment overlay between two layers of a semiconductor wafer. An incident beam of radiation is directed upon the wafer surface and the properties of the resulting diffracted beam are determined, in one embodiment as a function of wavelength or incident angle. The spectrally or angularly resolved characteristics of the diffracted beam are related to the alignment of the overlay features. A library of calculated diffraction spectra is established by modeling a full range of expected variations in overlay alignment. The spectra resulting from the inspection of an actual wafer having alignment targets in at least two layers is compared against the library to identify a best fit to characterize the actual alignment. The results of the comparison may be used as an input for upstream and/or downstream process control.

Abstract: A method (40) for nondestructively characterizing a doped region (24) of a semiconductor wafer (22) in order to determine the acceptability of a pattern transfer process. Of particular interest is the determination of the lateral profile of the implanted structure. An incident beam (28) of radiation is directed upon the wafer surface (26) and the properties of the resulting refracted beam (30) are measured as a function of wavelength. The spectrally-resolved diffraction characteristics of the refracted beam are directly related to the shape and scale characteristics of the doped region. A library (44) of calculated diffraction spectra is established by modeling a full range of expected variations in the doped region structures. The spectra resulting from the inspection of an actual doped region (46) is compared against the library to identify a best fit (48) in order to characterize the actual implant (50).

Abstract: A method of forming round corners for a gate oxide between a floating gate and a control gate of a memory cell comprises the steps of forming the floating gate over a tunnel oxide; forming a mask over the floating gate; forming rounded end caps adjacent distal ends of the mask; transferring the rounding of the end caps to top corners of the floating gate; forming the gate oxide over the floating gate; and, forming the control gate over the gate oxide. A memory cell having a rounded corner interface between the floating gate and control gate is also provided.

Abstract: The present invention provides a method for cleaning a contaminated chamber used in the manufacture of semiconductor devices. In one embodiment, the method comprises the steps of injecting, under pressure, a gas mixture of a fluorine-containing gas and an inert gas into the contaminated chamber, radiating the contaminated chamber with a radio frequency during the step of injecting, and removing volatile by-products or solid particulates from the contaminated chamber by performing pump-purge cycles within the contaminated chamber.

Abstract: A method of shallow trench isolation by forming a trench in a semiconductor device comprises the steps of forming an oxide layer; forming a mask layer; anisotropically etching the mask layer; forming a second oxide layer; forming a cap layer; forming rounded end caps adjacent the mask; and transferring the rounding of the caps to the top corners of the trench. The oxide layer is formed over a substrate of the semiconductor device. The mask layer is formed over the oxide layer. The mask layer is then anisotropically etched to form the mask and an opening in the mask. The opening in the mask exposes the substrate, and the width of the opening is greater than the width of the trench. Blanket etching the cap layer forms the rounded end caps. The rounded end caps are adjacent to the mask on opposite ends of the opening, and the distance between the end caps is about equal to the width of the trench. The trench is formed by plasma etching the trench.