Abstract: A method, apparatus and product performing feature vector aggregation for malware detection. Two sets of measurements produced by a two dynamic analyses of an examined program are obtained, wherein the two dynamic analyses are performed with respect to the examined program executing two different execution paths. An aggregated feature vector representing the examined program is generated. The aggregated feature vector comprises a set of aggregated features, wherein a value of each aggregated feature is based on an aggregation of corresponding measurements in the first set of measurements and in the second set of measurements. A predictive model is applied on the aggregated feature vector to classify the examined program as malicious or benign.

Abstract: A method, apparatus and product performing feature vector aggregation for malware detection. Two sets of measurements produced by a two dynamic analyses of an examined program are obtained, wherein the two dynamic analyses are performed with respect to the examined program executing two different execution paths. An aggregated feature vector representing the examined program is generated. The aggregated feature vector comprises a set of aggregated features, wherein a value of each aggregated feature is based on an aggregation of corresponding measurements in the first set of measurements and in the second set of measurements. A predictive model is applied on the aggregated feature vector to classify the examined program as malicious or benign.

Abstract: A computer-implemented method for verifying a target system includes defining a specification including properties applicable to the target system. Execution sequences of the target system are identified. A set of the execution sequences is grouped into an equivalence class characterized by a common control flow. A symbolic representation of the equivalence class is evaluated so as to verify a compliance of the set of the execution sequences with one or more of the properties.

Abstract: An apparatus includes a multi-cycle clock gater and a circuit design updater. The multi-cycle clock gater generates multi-cycle gating groups of data latching devices of a circuit design. The circuit design updater updates the circuit design with selected multi-cycle gating groups. Each gating group is associated with a single gating function. For each gating group, data latching devices of 0th level of the gating group are gated with the gating function and ith level data latching devices of the gating function are gated with ith latched versions of the gating function.

Abstract: Given a function F of a circuit having a data latching device and a feedback loop feeding an output Q of the device into logic which feeds the device, a method includes extracting at least one data independent case and clock-gating the device with the at least one data independent case. The method also includes eliminating the feedback loop if function F depends only on Q with a positive polarity or leaving the feedback loop if function F depends on Q in both positive and negative polarities.