Abstract: A data communications receiver for use in a modem. A fixed sample clock and a dominated tap tracking algorithm lock the local baud timing in the receiver to the baud timing in a remote transmitter. An interpolating filter provides a plurality of discrete delays. A filter control circuit inspects the tap coefficients of an adaptive equalizer to determine the location of and any movement of the dominant tap. The filter control circuit selects the rate of cycling through the discrete delays to compensate for any frequency difference between the local baud timing and the remote baud timing, and to prevent movement of the dominant tap. A baud detector circuit monitors the sample clock and the operating state of the filter control circuit to identify the end of a baud and detects and corrects for any frequency difference between the remote baud timing and the local baud timing by providing one additional sample or one less sample to the adaptive equalizer.

Abstract: A modem and an improved phase-locked loop used in the modem. A presettable counter (251) generates the desired signal (TXCLKOUT). The reference input clock signal (TXCLKIN) and the generated clock signal (TXCLKOUT) are compared by an exclusive-OR gate (254). The output of the gate (254) is sampled by two flip-flops (256,266) before and after a rising edge of the TXCLKOUT signal. If the TXCLKIN and TXCLKOUT signals differ by more than a desired phase window a logic circuit (264) adjusts the preset inputs of the counter (251) so that the TXCLKIN and TXCLKOUT signals are in phase within the desired phase window.