Abstract: The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redundant column drivers distributed throughout memory banks and flexibly selectable to replace faulty columns within multiple blocks within a bank; and switch means for selectively activating the redundant column and preventing the activation of a defective normal column, whereby the column redundancy method and apparatus minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required to be blown in repairing faulty columns addresses.

Abstract: A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle.

Abstract: A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle.