Abstract: Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, whose execution comprises, based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.

Abstract: A computer implemented instruction is executed. One or more translation table entry locations (TLB) are specified by the instruction. Based on a local-clearing (LC) control specified by the instruction being a first value, the processor selectively clears TLBs in a plurality of the CPUs in a configuration of entries corresponding to the determined translation table entry location. Based on the local-clearing (LC) being a second value, the processor selectively clears only the TLBs of the CPU executing the instruction of entries corresponding to the determined translation table entry location. A computer program product, computer system and computer implemented method are provided.

Abstract: Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, which comprises based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.

Abstract: A first and a second operand are compared. If they are equal, the contents of register R1+1 are stored at the second-operand location, and the specified CPU or CPUs in the configuration are cleared of all TLB table entries of the designated type formed through the use of the replaced entry in storage, and all lower-level TLB table entries formed through the use of the cleared higher-level TLB table entries. A valid DAT table entry is replaced with a new entry, and the Translation Lookaside Buffer (TLB) is purged of any copies of (at least) the single entry on all CPUs in the configuration. If the first and second operands are unequal, the second operand is loaded at the first-operand location. The comparison result is indicated by the condition code. A method, system and a computer program product are provided.

Abstract: A computer implemented instruction is executed. One or more translation table entry locations (TLB) are specified by the instruction. Based on a local-clearing (LC) control specified by the instruction being a first value, the processor selectively clears TLBs in a plurality of the CPUs in a configuration of entries corresponding to the determined translation table entry location. Based on the local-clearing (LC) being a second value, the processor selectively clears only the TLBs of the CPU executing the instruction of entries corresponding to the determined translation table entry location. A computer program product, computer system and computer implemented method are provided.

Abstract: One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions.

Abstract: A computer program product is provided for performing an input/output (I/O) processing operation at a host computer system. The computer program product is configured to perform: obtaining a transport command word (TCW) at a channel subsystem for an I/O operation, the TCW including an address of a transport command control block (TCCB) having a transport command area (TCA) configured to hold a first plurality of device command words (DCW) and control data associated with respective DCWs, the first plurality of DCWs including a transfer TCA extension (TTE) DCW that specifies a TCA extension, the TCA extension configured to hold one or more DCWs and control data associated with respective DCWs; gathering the TCCB from one or more locations specified in the TCCB address and transferring the TCCB to the control unit; gathering the TCA extension specified by the TTE DCW; and transferring the TCA extension to the control unit.

Abstract: Automatically converting a synchronous data transfer to an asynchronous data transfer. Data to be transferred from a sender to a receiver is initiated using a synchronous data transfer protocol. Responsive to a determination that the data is to be sent asynchronously, the data transfer is automatically converted from the synchronous data transfer to the asynchronous data transfer.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used.

Abstract: A computer program product is provided for performing an input/output (I/O) processing operation at a host computer system. The computer program product is configured to perform: obtaining a transport command word (TCW) at a channel subsystem for an I/O operation, the TCW including an address of a transport command control block (TCCB) having a transport command area (TCA) configured to hold a first plurality of device command words (DCW) and control data associated with respective DCWs, the first plurality of DCWs including a transfer TCA extension (TTE) DCW that specifies a TCA extension, the TCA extension configured to hold one or more DCWs and control data associated with respective DCWs; gathering the TCCB from one or more locations specified in the TCCB address and transferring the TCCB to the control unit; gathering the TCA extension specified by the TTE DCW; and transferring the TCA extension to the control unit.

Abstract: Automatically converting a synchronous data transfer to an asynchronous data transfer. Data to be transferred from a sender to a receiver is initiated using a synchronous data transfer protocol. Responsive to a determination that the data is to be sent asynchronously, the data transfer is automatically converted from the synchronous data transfer to the asynchronous data transfer.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.