Abstract: A method of providing a backdoor interface between software executing in a virtual machine and a hypervisor executing on a computing system that supports the virtual machine includes trapping, at the hypervisor, an exception generated in response to execution of a debug instruction on a central processing unit (CPU) by the software; identifying, by an exception handler of the hypervisor handling the exception, an equivalence between an immediate operand of the debug instruction and a predefined value; and invoking, in response to the equivalence, a backdoor service of the hypervisor using state of at least one register of the CPU as parametric input, the state being set by the software prior to executing the debug instruction.

Abstract: An example method of memory management in a virtualized computing system includes: generating a page table hierarchy that includes address translations to first pages of memory that store kernel software and second pages of the memory that store user software; configuring a processor to: 1) implement a first address translation scheme, which uses a first virtual address width, for a hypervisor privilege level; 2) implement a second address translation scheme, which uses a second virtual address width, for supervisor and user privilege levels, where the first virtual address width is larger than the second virtual address width; and 3) use the page table hierarchy for each of the first and second address translation schemes; and executing the kernel software at the hypervisor privilege level and the user software at the user privilege level.

Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

Abstract: An example method of memory management in a virtualized computing system includes: generating a page table hierarchy that includes address translations to first pages of memory that store kernel software and second pages of the memory that store user software; configuring a processor to: 1) implement a first address translation scheme, which uses a first virtual address width, for a hypervisor privilege level; 2) implement a second address translation scheme, which uses a second virtual address width, for supervisor and user privilege levels, where the first virtual address width is larger than the second virtual address width; and 3) use the page table hierarchy for each of the first and second address translation schemes; and executing the kernel software at the hypervisor privilege level and the user software at the user privilege level.

Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a PNMI, executing a PNMI interrupt handler. If the received interrupt is a regular interrupt, the method further comprises reading a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further: if the mask flag indicates that regular interrupts are enabled, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing, a regular interrupt handler, and disabling interrupts in the processor; and if the mask flag indicates that regular interrupts are disabled, saving the interrupt vector for subsequent handling.

Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes the steps of obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a regular interrupt, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector, and disabling interrupts in the processor. On the other hand, if the received interrupt is a PNMI, a PNMI interrupt handler is executed using the interrupt vector as an input thereto.

Abstract: An example method of initializing a plurality of processors in a hardware platform of computing device for use by system software executing on the hardware platform includes: parsing a descriptor table that has been loaded into memory from firmware to identify an original boot protocol for initializing at least one secondary processor of the plurality of processors; creating at least one mailbox structure in the memory associated with the at least one secondary processor; causing the at least one secondary processor to execute secondary processor initialization code stored in the memory, the secondary processor initialization code implementing a mailbox-based boot protocol that uses the at least one mailbox structure to initialize the at least one secondary processor; and modifying the descriptor table to identify the mailbox-based boot protocol for initializing the at least one secondary processor in place of the original boot protocol.

Abstract: A method of providing a backdoor interface between software executing in a virtual machine and a hypervisor executing on a computing system that supports the virtual machine includes trapping, at the hypervisor, an exception generated in response to execution of a debug instruction on a central processing unit (CPU) by the software; identifying, by an exception handler of the hypervisor handling the exception, an equivalence between an immediate operand of the debug instruction and a predefined value; and invoking, in response to the equivalence, a backdoor service of the hypervisor using state of at least one register of the CPU as parametric input, the state being set by the software prior to executing the debug instruction.

Abstract: Methods and systems configured to virtualize graphic processing services in a virtual machine environment are disclosed. A virtual machine monitor (VMM) may be configured to maintain a virtual machine (VM) based on a host operating system (OS) executing in the system. The VM may contain a virtualized graphics library (vGLib) configured to support a graphic command from an application executing in the VM. The host OS may contain a graphics library (GLib) configured to support the graphic command and utilize a graphics processing unit (GPU) in the system to process the graphic command. Upon receiving the graphic command from the application, the vGLib may be configured to allocate a memory section in the VM to store the graphic command. And the VMM may be further configured to share access to the memory section with the host OS, thereby allowing the host OS to retrieve the graphic command from the memory section and deliver the graphic command to the GLib for processing.

Abstract: A computer system provides a mechanism for assuring a safe, non-preemptible access to a private data area (PRDA) belonging to a CPU. PRDA accesses generally include obtaining an address of a PRDA and performing operations on the PRDA using the obtained address. Safe, non-preemptible access to a PRDA generally ensures that a context accesses the PRDA of the CPU on which the context is executing, but not the PRDA of another CPU. While a context executes on a first CPU, the context obtains the address of the PRDA. After the context is migrated to a second CPU, the context performs one or more operations on the PRDA belonging to the second CPU using the address obtained while the context executed on the first CPU. In another embodiment, preemption and possible migration of a context from one CPU to another CPU is delayed while a context executes non-preemptible code.

Abstract: In an example, a computer system includes a hardware platform and a hypervisor executing on the hardware platform. The hypervisor includes a kernel and a plurality of user-space instances within a user-space above the kernel. Each user-space instance is isolated from each other user-space instance through namespaces. Each user-space instance includes resources confined by hierarchical resource groups. The computer system includes a plurality of virtual hypervisors, where each virtual hypervisor executes in a respective user-space instance of the plurality of user-space instances.

Abstract: Methods and systems configured to virtualize graphic processing services in a virtual machine environment are disclosed. A virtual machine monitor (VMM) may be configured to maintain a virtual machine (VM) based on a host operating system (OS) executing in the system. The VM may contain a virtualized graphics library (vGLib) configured to support a graphic command from an application executing in the VM. The host OS may contain a graphics library (GLib) configured to support the graphic command and utilize a graphics processing unit (GPU) in the system to process the graphic command. Upon receiving the graphic command from the application, the vGLib may be configured to allocate a memory section in the VM to store the graphic command. And the VMM may be further configured to share access to the memory section with the host OS, thereby allowing the host OS to retrieve the graphic command from the memory section and deliver the graphic command to the GLib for processing.

Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a PNMI, executing a PNMI interrupt handler. If the received interrupt is a regular interrupt, the method further comprises reading a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further: if the mask flag indicates that regular interrupts are enabled, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing, a regular interrupt handler, and disabling interrupts in the processor; and if the mask flag indicates that regular interrupts are disabled, saving the interrupt vector for subsequent handling.

Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes the steps of obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a regular interrupt, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector, and disabling interrupts in the processor. On the other hand, if the received interrupt is a PNMI, a PNMI interrupt handler is executed using the interrupt vector as an input thereto.

Abstract: One embodiment of the present invention provides a system that facilitates storing an image file of a virtual machine on a potentially unprotected flash storage exhibiting sub-optimal non-sequential write performance on a mobile phone. During operation, the system stores in the flash storage data in a log-structured format and in a protected storage meta-data associated with the data stored in the flash storage. The system also checks integrity of the data stored in the flash storage using the meta-data in the protected storage.

Abstract: Machine memory fragmentation in a computer system having a host operating system and virtual machine running on a hypervisor hosted by the host operating system is reduced by having the hypervisor identify and release those machine memory pages that are more likely than others to reduce the fragmented state of the host machine memory.

Abstract: A computing device employs a cooperative memory management technique to dynamically balance memory resources between host and guest systems running therein. According to this cooperative memory management technique, memory that is allocated to the guest system is dynamically adjusted up and down according to a fairness policy that takes into account various factors including the relative amount of readily freeable memory resources in the host and guest systems and the relative amount of memory allocated to hidden applications in the host and guest systems.

Abstract: Methods and systems configured to virtualize graphic processing services in a virtual machine environment are disclosed. A virtual machine monitor (VMM) may be configured to maintain a virtual machine (VM) based on a host operating system (OS) executing in the system. The VM may contain a virtualized graphics library (vGLib) configured to support a graphic command from an application executing in the VM. The host OS may contain a graphics library (GLib) configured to support the graphic command and utilize a graphics processing unit (GPU) in the system to process the graphic command. Upon receiving the graphic command from the application, the vGLib may be configured to allocate a memory section in the VM to store the graphic command. And the VMM may be further configured to share access to the memory section with the host OS, thereby allowing the host OS to retrieve the graphic command from the memory section and deliver the graphic command to the GLib for processing.

Abstract: A computing device employs a cooperative memory management technique to dynamically balance memory resources between host and guest systems running therein. According to this cooperative memory management technique, memory that is allocated to the guest system is dynamically adjusted up and down according to a fairness policy that takes into account various factors including the relative amount of readily freeable memory resources in the host and guest systems and the relative amount of memory allocated to hidden applications in the host and guest systems.

Abstract: One embodiment of the present invention provides a system that facilitates storing an image file of a virtual machine on a potentially unprotected flash storage exhibiting sub-optimal non-sequential write performance on a mobile phone. During operation, the system stores in the flash storage data in a log-structured format and in a protected storage meta-data associated with the data stored in the flash storage. The system also checks integrity of the data stored in the flash storage using the meta-data in the protected storage.