Patents by Inventor Cyril Cabral, Jr.
Cyril Cabral, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160163658Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.Type: ApplicationFiled: February 15, 2016Publication date: June 9, 2016Inventors: Cyril Cabral, JR., Gregory M. Fritz, Conal E. Murray, Kenneth P. Rodbell
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Publication number: 20160137548Abstract: A method of manufacturing a glass substrate to control the fragmentation characteristics by etching and filling trenches in the glass substrate is disclosed. An etching pattern may be determined. The etching pattern may outline where trenches will be etched into a surface of the glass substrate. The etching pattern may be configured so that the glass substrate, when fractured, has a smaller fragmentation size than chemically strengthened glass that has not been etched. A mask may be created in accordance with the etching pattern, and the mask may be applied to a surface of the glass substrate. The surface of the glass substrate may then be etched to create trenches. A filler material may be deposited into the trenches.Type: ApplicationFiled: April 30, 2015Publication date: May 19, 2016Inventors: Cyril Cabral, JR., Fuad E. Doany, Gregory M. Fritz, Michael S. Gordon, Qiang Huang, Eric P. Lewandowski, Xiao Hu Liu, Kenneth P. Rodbell, Thomas M. Shaw
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Publication number: 20160133581Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.Type: ApplicationFiled: November 6, 2014Publication date: May 12, 2016Inventors: Cyril Cabral, Jr., Gregory M. Fritz, Conal E. Murray, Kenneth P. Rodbell
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Patent number: 9299665Abstract: A structure fabrication method. An integrated circuit that includes N chip electric pads is bonded to a top side of an interposing shield that includes N electric conductors. N is at least 2. The interposing shield includes a shield material that includes a first semiconductor material. A bottom side of the interposing shield is polished, which exposes the N electric conductors to a surrounding ambient. The bonding includes bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact and direct physical contact with corresponding electrical pads of the N electric conductors. The shield material covers the N electric conductors in a manner that the N electric conductors are not exposed to the surrounding ambient. The polishing removes a sufficient amount of the shield material to expose the N electric conductors to the surrounding ambient.Type: GrantFiled: October 21, 2014Date of Patent: March 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Paul S. Andry, Cyril Cabral, Jr., Kenneth P. Rodbell, Robert L. Wisnieff
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Patent number: 9299638Abstract: Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers.Type: GrantFiled: December 6, 2012Date of Patent: March 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Cyril Cabral, Jr., Sebastian U. Engelmann, Benjamin L. Fletcher, Michael S. Gordon, Eric A. Joseph
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Patent number: 9299639Abstract: An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers.Type: GrantFiled: January 4, 2013Date of Patent: March 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Cyril Cabral, Jr., Sebastian U. Engelmann, Benjamin L. Fletcher, Michael S. Gordon, Eric A. Joseph
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Patent number: 9263393Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.Type: GrantFiled: May 14, 2015Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Cyril Cabral, Jr., Benjamin L. Fletcher, Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe
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Publication number: 20150348832Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicant: International Business Machines CorporationInventors: Robert L. Bruce, Cyril Cabral, JR., Gregory M. Fritz, Eric A. Joseph, Michael F. Lofaro, Hiroyuki Miyazoe, Kenneth P. Rodbell, Ghavam G. Shahidi
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Publication number: 20150340323Abstract: Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mx level including an Mx metal in an Mx dielectric, an Mx+1 level above the Mx level including an Mx+1 metal in an Mx+1 dielectric, an embedded diffusion barrier adjacent to the Mx+1 dielectric; and a seed alloy region adjacent to the Mx+1 metal separating the Mx metal from the Mx+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.Type: ApplicationFiled: August 4, 2015Publication date: November 26, 2015Inventors: Cyril Cabral, JR., Daniel C. Edelstein, Juntao Li, Takeshi Nogami
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Patent number: 9190321Abstract: Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mx level including an Mx metal in an Mx dielectric, an Mx+1 level above the Mx level including an Mx+1 metal in an Mx+1 dielectric, an embedded diffusion barrier adjacent to the Mx+1 dielectric; and a seed alloy region adjacent to the Mx+1 metal separating the Mx metal from the Mx+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.Type: GrantFiled: April 8, 2013Date of Patent: November 17, 2015Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Daniel C. Edelstein, Juntao Li, Takeshi Nogami
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Patent number: 9166014Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.Type: GrantFiled: June 6, 2013Date of Patent: October 20, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Nicolas L. Breil, Cyril Cabral, Jr., Martin M. Frank, Claude Ortolland
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Publication number: 20150243602Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.Type: ApplicationFiled: May 14, 2015Publication date: August 27, 2015Inventors: Cyril Cabral, JR., Benjamin L. Fletcher, Nicholas C.M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe
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Publication number: 20150194355Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.Type: ApplicationFiled: January 6, 2014Publication date: July 9, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril CABRAL, Jr., Lawrence A. CLEVENGER, John M. COHN, Jeffrey P. GAMBINO, William J. MURPHY, Anthony J. TELENSKY
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Patent number: 9064727Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.Type: GrantFiled: August 20, 2013Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Benjamin L. Fletcher, Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe
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Publication number: 20150171023Abstract: A structure fabrication method. An integrated circuit that includes N chip electric pads is bonded to a top side of an interposing shield that includes N electric conductors. N is at least 2. The interposing shield includes a shield material that includes a first semiconductor material. A bottom side of the interposing shield is polished, which exposes the N electric conductors to a surrounding ambient. The bonding includes bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact and direct physical contact with corresponding electrical pads of the N electric conductors. The shield material covers the N electric conductors in a manner that the N electric conductors are not exposed to the surrounding ambient. The polishing removes a sufficient amount of the shield material to expose the N electric conductors to the surrounding ambient.Type: ApplicationFiled: October 21, 2014Publication date: June 18, 2015Inventors: Paul S. Andry, Cyril Cabral, JR., Kenneth P. Rodbell, Robert L. Wisnieff
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Patent number: 9034749Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.Type: GrantFiled: September 12, 2013Date of Patent: May 19, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicolas L. Breil, Cyril Cabral, Jr., Martin M. Frank, Claude Ortolland
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Publication number: 20150054092Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.Type: ApplicationFiled: November 5, 2014Publication date: February 26, 2015Inventors: Guy Cohen, Cyril Cabral, JR., Anirban Basu
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Patent number: 8941123Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.Type: GrantFiled: May 30, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Guy Cohen, Cyril Cabral, Jr., Anirban Basu, Jr.
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Patent number: 8928145Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.Type: GrantFiled: June 26, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Cyril Cabral, Jr., Kenneth P. Rodbell, Robert L. Wisnieff
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Publication number: 20140363964Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.Type: ApplicationFiled: September 12, 2013Publication date: December 11, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicolas L. Breil, Cyril Cabral, JR., Martin M. Frank, Claude Ortolland