Patents by Inventor Cyril de la Cropte de Chanterac

Cyril de la Cropte de Chanterac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190326776
    Abstract: Examples of the disclosure are directed to methods of managing power of various modules of an electronic device to prevent the voltage of the battery from falling to an undervoltage lockout (UVLO) threshold. In some examples, software operating on the electronic device or an associated electronic device (e.g., a paired electronic device) may assign power budgets to one or more modules, thereby preventing each module from drawing its maximum current capacity and causing the battery's voltage level to fall to the UVLO threshold. In some examples, a pre-UVLO threshold (i.e., a threshold higher than the UVLO threshold) may be used to modify the states of one or more modules to save power as the voltage of the battery approaches the UVLO threshold, but before the device must be fully powered off.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Cyril DE LA CROPTE DE CHANTERAC, David A. HARDELL, Matthew L. SEMERSKY, Yehonatan PEREZ
  • Patent number: 10448338
    Abstract: An example computer-implemented method includes determining, by an electronic device, that the electronic device has not received a user activity for an interval of time. The method also includes determining, by the electronic device, a contextual state of the electronic device, and adapting, by the electronic device, a sleep delay value based on the determined contextual state of the electronic device. The method also includes determining that the interval of time has exceeded the sleep delay value, and responsive to determining that the interval of time has exceeded the sleep delay value, transitioning, by the electronic device, from a first power state to a second power state, where the first power state is higher or lower than the second power state.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: October 15, 2019
    Assignee: Apple Inc.
    Inventors: Gaurav Kapoor, Andrei Dorofeev, Varaprasad V. Lingutla, Cyril de la Cropte de Chanterac
  • Patent number: 10437313
    Abstract: Embodiments provide for a computer implemented method comprising sampling one or more power and performance metrics of a processor; determining an energy cost per instruction based on the one or more power and performance metrics; determining an efficiency metric based on the energy cost per instruction; computing an efficiency control error based on a difference between a current efficiency metric and a target efficiency metric; setting an efficiency control effort based on the efficiency control error; determining a performance control effort, the performance control effort determined by a performance controller for the processor; and adjusting the performance control effort based on the efficiency control effort, wherein adjusting the performance control effort reduces power consumption of the processor.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 8, 2019
    Inventors: John G. Dorsey, Christopher W. Chaney, Norman J. Rohrer, Cyril De La Cropte De Chanterac
  • Patent number: 10437639
    Abstract: In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: October 8, 2019
    Assignee: Apple Inc.
    Inventors: Russell A. Blaine, Daniel A. Chimene, Shantonu Sen, John Dorsey, Bryan Hinch, Cyril De La Cropte De Chanterac, Oliver Cozette
  • Patent number: 10417054
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 17, 2019
    Assignee: Apple Inc.
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
  • Publication number: 20190266593
    Abstract: This application relates to systems, methods, and apparatus for using a computing device to perform payment transactions while the computing device is operating in a low power wallet mode during a low battery state of the computing device. During a low power wallet mode, various subsystems are prevented from receiving current from a battery of the computing device, while a near field communication (NFC) system of the computing device is provided with an operating current for detecting target systems. A target system and the NFC system can communicate during the low power wallet mode of the computing device, thereby allowing a user of the computing device to conduct payment transactions when the computing device is in a low power wallet mode. Such payment transactions can be useful if the user is ever stranded without enough power to fully operate the computing device and needs to pay for transportation.
    Type: Application
    Filed: December 20, 2018
    Publication date: August 29, 2019
    Inventors: Cyril de la Cropte de Chanterac, Joseph Hakim, Leland W. Lew, Hue Duc Tran
  • Publication number: 20190179404
    Abstract: Examples of the disclosure are directed to a method of, after hitting a UVLO threshold, rebooting an electronic device in a low power mode having a lower UVLO threshold, such that the device can continue to be used past the first UVLO threshold. For example, in a high power mode, the device may be capable of a number of functionalities of a modern portable electronic device, such as network access, the ability to run applications, Bluetooth connections, etc. In a low power mode, the device may only be able to check and display a current time, play an alarm sound at a predefined time, perform near field communication (NFC) transactions/payments, among other possibilities described herein. The limited functionality and reduced usage of peripherals in the low power mode may prevent the battery from experiencing peaks in current level that may be problematic at relatively low levels of voltage.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 13, 2019
    Inventors: Jonathan J. ANDREWS, Cyril DE LA CROPTE DE CHANTERAC, Eugene KIM
  • Patent number: 10310586
    Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 4, 2019
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Shinye Shiu, Cyril de la Cropte de Chanterac, Manu Gulati, Pulkit Desai, Rong Zhang Hu
  • Patent number: 10228751
    Abstract: Examples of the disclosure are directed to a method of, after hitting a UVLO threshold, rebooting an electronic device in a low power mode having a lower UVLO threshold, such that the device can continue to be used past the first UVLO threshold. For example, in a high power mode, the device may be capable of a number of functionalities of a modern portable electronic device, such as network access, the ability to run applications, Bluetooth connections, etc. In a low power mode, the device may only be able to check and display a current time, play an alarm sound at a predefined time, perform near field communication (NFC) transactions/payments, among other possibilities described herein. The limited functionality and reduced usage of peripherals in the low power mode may prevent the battery from experiencing peaks in current level that may be problematic at relatively low levels of voltage.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: March 12, 2019
    Assignee: Apple Inc.
    Inventors: Jonathan J. Andrews, Cyril De La Cropte De Chanterac, Eugene Kim
  • Publication number: 20190075037
    Abstract: In some implementations, a user device can schedule tasks based on user behavior. For example, the user device can receive a task request that includes a time window and user/device context parameters for performing the task. The user device can predict a time when the user/device context is optimal for performing the task during the time window based on historical context data. For example, the user device can generate an optimal context score for the task based on the context parameters and the historical context data. The user device can execute the requested task at a current time within the time window when a context score for the current context exceeds a threshold determined based on the optimal context score.
    Type: Application
    Filed: November 5, 2018
    Publication date: March 7, 2019
    Applicant: Apple Inc.
    Inventors: Kartik Venkatraman, Cyril de la Cropte de Chanterac, Shardul Mangade
  • Publication number: 20190057007
    Abstract: Systems and methods are disclosed for advising a user when an energy storage device in a computing system needs charging. State of charge data of the energy storage device can be measured and stored at regular intervals. The historic state of charge data can be queried over a plurality of intervals and a state of charge curve generated that is representative of a user's charging habits over time. The state of charge curve can be used to generate a rate of charge histogram and an acceleration of charge histogram. These can be used to predict when a user will charge next, and whether the energy storage device will have an amount of energy below a predetermined threshold amount before the next predicted charging time. A first device can determine when a second device typically charges and whether the energy storage device in the second device will have an amount of energy below the predetermined threshold amount before the next predicted charge time for the second device.
    Type: Application
    Filed: September 4, 2018
    Publication date: February 21, 2019
    Inventors: Cyril DE LA CROPTE DE CHANTERAC, Phillip STANLEY-MARBELL, Kartik VENKATRAMAN, Gaurav KAPOOR
  • Patent number: 10198726
    Abstract: This application relates to systems, methods, and apparatus for using a computing device to perform payment transactions while the computing device is operating in a low power wallet mode during a low battery state of the computing device. During a low power wallet mode, various subsystems are prevented from receiving current from a battery of the computing device, while a near field communication (NFC) system of the computing device is provided with an operating current for detecting target systems. A target system and the NFC system can communicate during the low power wallet mode of the computing device, thereby allowing a user of the computing device to conduct payment transactions when the computing device is in a low power wallet mode. Such payment transactions can be useful if the user is ever stranded without enough power to fully operate the computing device and needs to pay for transportation.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: February 5, 2019
    Assignee: APPLE INC.
    Inventors: Cyril de la Cropte de Chanterac, Joseph Hakim, Leland W. Lew, Hue Duc Tran
  • Publication number: 20180364786
    Abstract: An electronic device may have a power system with a battery. The power system receives power such as wireless power or wired power and uses a portion of the received power to charge the battery as needed. Control circuitry in the portable electronic device is used to run background processes such as image processing tasks, data synchronization tasks, indexing, and other background processes. In some circumstances, such as when the battery is below a certain state of charge threshold, background processes may be stopped so that the battery is charged as fast as possible. Once above this initial state of charge threshold, background processes may be performed during charging as long as the temperature and state of charge of the battery do not exceed safety temperature and safety state of charge values. Performing background processes in these conditions ensures requisite background processing tasks are completed while preserving battery health.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 20, 2018
    Inventors: Cyril de la Cropte de Chanterac, Kartik R. Venkatraman, Alessandro Pelosi, Shardul S. Mangade
  • Publication number: 20180349176
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 6, 2018
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
  • Publication number: 20180348849
    Abstract: This application relates to techniques that adjust the sleep states of a computing device based on proximity detection and predicted user activity. Proximity detection procedures can be used to determine a proximity between the computing device and a remote computing device coupled to the user. Based on these proximity detection procedures, the computing device can either correspondingly increase or decrease the amount power supplied to the various components during either a low-power sleep state or a high-power sleep state. Additionally, historical user activity data gathered on the computing device can be used to predict when the user will likely use the computing device. Based on the gathered historical user activity, deep sleep signals and light sleep signals can be issued at a time when the computing device is placed within a sleep state which can cause it to immediately enter either a low-power sleep state or a high-power sleep state.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 6, 2018
    Inventors: Varaprasad V. LINGUTLA, Kartik R. VENKATRAMAN, Cyril de la CROPTE de CHANTERAC, Bob BRADLEY, Marc J. KROCHMAL, Matthew D. PERKINS, Christopher S. LINN, Akshay MANGALAM SRIVATSA
  • Publication number: 20180349175
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 6, 2018
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol, James S. Ismail
  • Publication number: 20180349182
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 6, 2018
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
  • Publication number: 20180351390
    Abstract: An electronic device may have a power system. The power system may receive power such as wireless power or wired power and may use a portion of the received power to charge a battery. Power consumption by control circuitry in the device can be adjusted by deactivating or activating processor cores in the control circuitry and by selectively starting or stopping software activities. By selectively reducing power consumption by circuitry in the electronic device other than battery charging circuitry in the power system that is charging the battery, additional power may be made available to charge the battery and/or battery capacity can be extended. The electronic device may reduce non-battery-charging activities in the device in response to information gathered with sensors such as motion and temperature information, information from the power system, information on device location, information on software settings, and other information.
    Type: Application
    Filed: September 15, 2017
    Publication date: December 6, 2018
    Inventors: Kartik R. Venkatraman, Shardul S. Mangade, Alessandro Pelosi, Cyril de la Cropte de Chanterac
  • Publication number: 20180349186
    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 6, 2018
    Inventors: Jeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
  • Patent number: 10148546
    Abstract: In some implementations, a user device can schedule tasks based on user behavior. For example, the user device can receive a task request that includes a time window and user/device context parameters for performing the task. The user device can predict a time when the user/device context is optimal for performing the task during the time window based on historical context data. For example, the user device can generate an optimal context score for the task based on the context parameters and the historical context data. The user device can execute the requested task at a current time within the time window when a context score for the current context exceeds a threshold determined based on the optimal context score.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: December 4, 2018
    Assignee: APPLE INC.
    Inventors: Kartik Venkatraman, Cyril de la Cropte de Chanterac, Shardul Mangade