Abstract: A magnetoresistance element can have a substrate; a ferromagnetic seed layer consisting of a binary alloy of NiFe; and a first nonmagnetic spacer layer disposed under and directly adjacent to the ferromagnetic seed layer and proximate to the substrate, wherein the first nonmagnetic spacer layer is comprised of Ta or Ru. A method fabricating of fabricating a magnetoresistance element can include depositing a seed layer structure over a semiconductor substrate, wherein the depositing the seed layer structure includes depositing at least a ferromagnetic seed layer over the substrate. The method further can further include depositing a free layer structure over the seed layer structure, wherein the depositing the ferromagnetic seed layer comprises depositing the ferromagnetic seed layer in the presence of a motion along a predetermined direction and in the presence of a predetermined magnetic field having the same predetermined direction.

Abstract: A magnetoresistance element has a double pinned arrangement with two antiferromagnetic pinning layers, two pinned layers, and a free layer. A spacer layer between one of the two antiferromagnetic pinning layers and the free layer has a material selected to allow a controllable partial pinning by the one of the two antiferromagnetic pinning layers.

Abstract: A memory device including: one inert electrode including an electrically conductive material, a part of at least one material of resistivity higher than that of the material of the inert electrode, positioned around the inert electrode, a solid electrolyte positioned on at least one part of the inert electrode and of the part of electrically insulating material, and including metal ions originating from an ionizable metal part positioned on the solid electrolyte. The ratio between the coefficient of electrical resistivity of the material of resistivity higher than that of the material of the inert electrode and the coefficient of electrical resistivity of the material of the inert electrode is equal to or higher than approximately 100, and the coefficient of thermal conductivity of the electrically insulating material is equal to or higher than approximately 10 W·m?1·K?1.

Abstract: A magnetoresistance element has a double pinned arrangement with two antiferromagnetic pinning layers, two pinned layers, and a free layer. A spacer layer between one of the two antiferromagnetic pinning layers and the free layer has a material selected to allow a controllable partial pinning by the one of the two antiferromagnetic pinning layers.

Abstract: A magnetoresistance element has a seed layer that promotes an increased magnetic anisotropy of layers of the magnetoresistance element above the seed layer structure.

Abstract: The invention relates to a process for manufacturing a plurality of CBRAM memories, each comprising a memory cell in a chalcogenide solid electrolyte, an anode, and a cathode, the process comprising implementing a sublayer of a high thermal conductivity material, higher than 1.3 W/m/K, which covers the set of contacts, then providing, on said sublayer, a triple layer comprising a chalcogenide layer, then an anodic layer, and a layer with second contacts (36), and finally an etching step.

Abstract: A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte.

Abstract: A memory device including: one inert electrode including an electrically conductive material, a part of at least one material of resistivity higher than that of the material of the inert electrode, positioned around the inert electrode, a solid electrolyte positioned on at least one part of the inert electrode and of the part of electrically insulating material, and including metal ions originating from an ionizable metal part positioned on the solid electrolyte. The ratio between the coefficient of electrical resistivity of the material of resistivity higher than that of the material of the inert electrode and the coefficient of electrical resistivity of the material of the inert electrode is equal to or higher than approximately 100, and the coefficient of thermal conductivity of the electrically insulating material is equal to or higher than approximately 10 W·m?1·K?1.

Abstract: A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte.

Abstract: A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte.

Abstract: The invention relates to a process for manufacturing a plurality of CBRAM memories, each comprising a memory cell in a chalcogenide solid electrolyte, an anode, and a cathode, the process comprising implementing a sublayer of a high thermal conductivity material, higher than 1.3 W/m/K, which covers the set of contacts, then providing, on said sublayer, a triple layer comprising a chalcogenide layer, then an anodic layer, and a layer with second contacts (36), and finally an etching step.

Abstract: This invention relates to a microelectronic device provided with one or several cells or elements comprising at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode, said stack comprising: at least one doped chalcogenide layer that will form a solid electrolyte, on and in contact with the first electrode, at least one layer called the “interface” layer based on a given material different from said chalcogenide, on and in contact with said doped chalcogenide layer, at least one metallic layer called the “ion donor” layer, on and in contact with said “interface” layer, that will form an ion source for said solid electrolyte. The invention also relates to a method for making such a device.