Patents by Inventor Cyril Quennesson
Cyril Quennesson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9304881Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.Type: GrantFiled: October 16, 2013Date of Patent: April 5, 2016Assignee: Mentor Graphics CorporationInventors: Cyril Quennesson, Pamphile Koumou
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Publication number: 20140046650Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.Type: ApplicationFiled: October 16, 2013Publication date: February 13, 2014Applicant: Mentor Graphics CorporationInventors: Cyril Quennesson, Pamphile Koumou
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Patent number: 8566068Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.Type: GrantFiled: May 24, 2012Date of Patent: October 22, 2013Assignee: Mentor Graphics CorporationInventors: Cyril Quennesson, Pamphile Koumou
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Publication number: 20120232881Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.Type: ApplicationFiled: May 24, 2012Publication date: September 13, 2012Inventors: Cyril Quennesson, Pamphile Koumou
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Patent number: 8108198Abstract: A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory are captured in a second Random Access Memory. After the capturing, the contents of the second Random Access Memory are copied to a visibility system. During the copying, the user design may modify the data in the first Random Access Memory while the captured contents within the second Random Access Memory remain unmodifiable so that the captured contents are not compromised. In another aspect, different size memories are in the emulator to emulate the user model. Larger memories have their ports monitored to reconstruct the contents of the memories, while smaller memories are captured in a snapshot RAM. Together the two different modes of tracing memory are used to provide visibility to the user of the entire user memory.Type: GrantFiled: February 21, 2007Date of Patent: January 31, 2012Assignee: Mentor Graphics CorporationInventors: Peer Schmitt, Philippe Diehl, Charles Selvidge, Cyril Quennesson
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Patent number: 7924845Abstract: Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.Type: GrantFiled: September 30, 2003Date of Patent: April 12, 2011Assignee: Mentor Graphics CorporationInventors: Philippe Diehl, Marc Vieillot, Cyril Quennesson, Gilles Laurent, Frederic Reblewski
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Publication number: 20090259457Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.Type: ApplicationFiled: June 10, 2008Publication date: October 15, 2009Inventors: Cyril Quennesson, Pamphile Koumou
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Publication number: 20080288719Abstract: A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory are captured in a second Random Access Memory. After the capturing, the contents of the second Random Access Memory are copied to a visibility system. During the copying, the user design may modify the data in the first Random Access Memory while the captured contents within the second Random Access Memory remain unmodifiable so that the captured contents are not compromised. In another aspect, different size memories are in the emulator to emulate the user model. Larger memories have their ports monitored to reconstruct the contents of the memories, while smaller memories are captured in a snapshot RAM. Together the two different modes of tracing memory are used to provide visibility to the user of the entire user memory.Type: ApplicationFiled: February 21, 2007Publication date: November 20, 2008Inventors: Peer Schmitt, Philippe Diehl, Charles Selvidge, Cyril Quennesson
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Publication number: 20050068949Abstract: Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Inventors: Philippe Diehl, Marc Vieillot, Cyril Quennesson, Gilles Laurent, Frederic Reblewski
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Publication number: 20040254778Abstract: A novel reconfigurable logic element (RLE) architecture for use in an integrated circuit itself used in an emulation system is disclosed. The RLE has lookup table logic circuitry for implementing a function. In addition, the RLE contains multi-stage coupling logic circuitry correspondingly coupling RLE inputs to the inputs of the lookup table logic circuitry. This allows global routing of the emulation system by circuit design mapping software to be much more flexible, as the routing may be configured independently of those four input constraints due to the ability to reassign the inputs with the swapper.Type: ApplicationFiled: June 12, 2003Publication date: December 16, 2004Applicant: Mentor Graphics CorporationInventors: Gilles Laurent, Cyril Quennesson, Olivier Filoche