Patents by Inventor Cyrill Ponce

Cyrill Ponce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware-assisted DMA transfer with dependency table configured to permit-in parallel-data drain from cache without processor intervention when filled or drained
    Patent number: 9400617
    Abstract: The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. 1 Descriptors are set of instructions that is used to activate the DMA controller. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: July 26, 2016
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Cyrill Ponce, Marizonne Operio Fuentes, Gianico Geonzon Noble
  • Hardware-Assisted DMA Transfer with Dependency
    Publication number: 20150006766
    Abstract: The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. 1 Descriptors are set of instructions that is used to activate the DMA controller. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.
    Type: Application
    Filed: March 17, 2014
    Publication date: January 1, 2015
    Inventors: Cyrill Ponce, Marizone Operio Fuentes, Gianico Geonzon Noble