Abstract: A computer network is provided with a low-complexity sequence identification number determination method. In one embodiment, the computer network comprises a local node coupled to a remote node by a serial communications link to conduct data exchanges with the remote node. Each data exchange is provided with an exchange identification number, and each data exchange is made up of sequences of consecutive frames. Each sequence transmitted from the local node is assigned a sequence identification number by the local node. To maintain the uniqueness of the serial identification numbers of concurrently active sequences, a portion of each serial identification number is set equal to the exchange identification number of the data exchange of which the sequence is a part. The exchange identification number may be one assigned to the exchange by the remote node. In one implementation, the sequence identification number is a byte having the six most significant bits set equal to the exchange identification number.

Abstract: A memory interface for synchronous burst SRAMs is provided. In one embodiment, an information processing system comprises a processor and a memory coupled by a memory interface. The memory interface includes a left data latch and a right data latch. The left data latch latches and holds data provided by the memory until the processor accepts it. The right data latch latches and holds data provided by the memory if the left data latch is already latched. Each data latch is freed after its contents have been provided to the processor. A multiplexer is included to steer the least-recently latched data to the processor. The latches and multiplexer are controlled by an interface controller which tracks the state of the latches and the order in which they latched. The interface controller generates control signals in response to the state of the latches and signals from the processor and the memory.