Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: The present invention is to provide two methods for trimming output HSync in display timing conversion for digital display application, so that the scaling controller can minimize Line Buffer timing shift and match the VSync/HSync timing requirement of digital display device. “Horizontal synchronization vibration” and “Remapping” are the two methods of the present invention.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: The invention provides a system and method for mixing graphics and text in an on-screen display application. The system includes font and character memories. The font memory stores bitmaps associated with characters to be displayed on a display device. The character memory, in turn, includes a font portion and an attribute portion. The font portion stores a font index of characters to be displayed, the font index being used to address the font memory. The attribute portion stores a plurality of attributes associated with a character to be displayed. The plurality of attributes includes a text/graphic attribute indicative of a text character or a graphic clip and a redirection attribute indicating mapping of a main color memory using an expanded color memory.

Abstract: The present invention is to provide two methods for trimming output HSync in display timing conversion for digital display application, so that the scaling controller can minimize Line Buffer timing shift and match the VSync/HSync timing requirement of digital display device. “Horizontal synchronization vibration” and “Remapping” are the two methods of the present invention.

Abstract: The invention provides a system and method for providing a variable character size in an on-screen display application. The system includes logic means and a font memory means adapted to store a plurality of bitmaps corresponding to a plurality of characters. A mapping memory means is adapted to map the plurality of characters into the plurality of bitmaps. And a display means is adapted to display the plurality of bitmaps responsive to the logic means. The mapping memory comprises a width and a height associated with each of the plurality of characters. The mapping memory comprises a pointing means adapted to store an address associated with each of the plurality of bitmaps.

Abstract: A circuit and method are provided for initializing configuration registers in a bus bridge controller so that peripheral devices can acquire functionality prior to initialization by a normal system Basic Input/Output System (BIOS) routine. The initialization information is stored in a supplemental configuration Electronically Erasable Programmable Read Only Memory (EEPROM), separate from a conventional system BIOS ROM. In addition, the register configuration information is stored in a flexible format so that only certain devices are pre-configured, or that certain devices are initialized before others. The invention has particular usefulness in personal computing systems which include a Peripheral Component Interconnect (PCI) bus, an ISA bus, and a system management bus (SMB) for providing access to the EEPROM.