Abstract: An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal.

Abstract: An in-system programmable (ISP) system can be programmed by remote access from a host programming system. The remote access can be accomplished over a wired data network, a wireless data network, a radio channel, or any combination of the above. In the ISP system, an ISP controller receives control and programming data through the access interface to program ISP devices in accordance with ISP programming conventions. The ISP controller can be provided by an integrated circuit having a microprocessor core.

Abstract: An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.

Abstract: An in-system programmable (ISP) system can be programmed by remote access from a host programming system. The remote access can be accomplished over a wired data network, a wireless data network, a radio channel, or any combination of the above. In the ISP system, an ISP controller receives control and programming data through the access interface to program ISP devices in accordance with ISP programming conventions. The ISP controller can be provided by an integrated circuit having a microprocessor core.

Abstract: An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.

Abstract: An improved programmable logic device that generates output signals skewed in time includes a set of I/O cells and first and second logic circuits. Each logic circuit generates a logic output signal on a respective output line coupled to at least one of the I/O cells. A first delay element coupled to the output line of the first logic circuit is programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to a first delay control signal. A second delay element coupled to the output line of the second logic circuit is programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal. Control circuitry generates the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits.

Abstract: A method for minimizing instantaneous currents ina signal bus is disclosed. The method involves providing a programmable delay element in each of the signal buffers driving the signal on the bus. The programmable delay element in each signal buffer is selectable enabled to include a predetermined time delay. The method involves programming the delay elements in a selected group of the signal buffers t includde the predetermined time delay, so that the selected group of signal buffers each generate an output signal switching after the predetermined delay relative to the switching of output signals generated by other signal buffers.

Abstract: An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal.

Abstract: A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.

Abstract: A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portion of the programmable logic device.

Abstract: A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portions of the programmable logic device.

Abstract: An improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a plurality of I/O cells and a plurality of logic block clusters. Each logic block cluster has a set of logic blocks and a cluster routing pool, which provides programmable connections among the logic blocks and the I/O cells. A global routing pool provides programmable connections among the logic block clusters and the I/O cells. Each logic block includes a programmable logic array with a plurality of outputs. A product term sharing array in the logic block has a plurality of bus lines, each of which is coupled to at least one of the outputs of the programmable logic array. The product term sharing array also includes a plurality of output lines, each of which is coupled to a plurality of programmable interconnections that each provide a connection to one of the bus lines. Each output line of the product term sharing array is coupled to the same number of programmable interconnections.

Abstract: A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal.

Abstract: A programmable interconnect circuit includes multiple input/output cells, each corresponding to an input/output pin, and a global routing resource for routing signals received at the input pins to be output as output signals at output and bi-directional pins. The signals routed in the global routing resource can include multiplexer control signals, clock signals and output enable signals for controlling dynamic signal switching. The global routing resource allows high static routability.

Abstract: An in-system programmable (ISP) system, having a plurality of ISP devices, can be programmed by remote access from a host controller. The remote access can be accomplished over a wired data network, a wireless data network such as an infra-red data network and a radio wave data network, or a hybrid network including both a wired data network portion and a wireless data network portion. An access interface connects the host controller to an ISP programmer over the wired or wireless communication link. The ISP programmer programs the ISP system in accordance with ISP programming conventions. The ISP programmer can be provided by an integrated circuit having a microprocessor core.

Abstract: A structure and a method provide a programmable logic device including a number of generic logic blocks and one or more application-specific block. Such application-specific block implements a specific function, such as a register file or a memory array. In one embodiment, the application specific block is programmable to be either one or more single-port memory array, a first-in-first-out (FIFO) memory, or a dual port memory array. In another embodiment, the application-specific block can be configured to be a register file, a number of counters, a number of timers, or a shift register. The application-specific block can be used in conjunction with programmable logic arrays for multiplexing input and output signals into and out of the application-specific block. Interconnectivity between the generic logic blocks and the application-specific blocks using a global routing resource integrates into a programmable logic device functions otherwise difficult to implement using only generic logic blocks.

Abstract: An output enable structure and a method for providing output capability to an input/output cell of a programmable logic device are shown. In one embodiment, one of two global output enable signals, a test output enable signal, and two product term output enable signals is selected for controlling an output buffer of an I/O cell. Additional pin-out flexibility is provided by routing the input signal received at an I/O pin to neighboring I/O cells.

Abstract: A structure and a method to implement in-system programming (ISP) and boundary-scan testing in an integrated circuit using the same pins to control both functions. The SDI, SCLK, MODE and SDO connections required for in-system programming and the TDI, TCK, TMS and TDO connections required for boundary-scan testing are multiplexed such that they are provided from the same four pins. An in-system programming enable pin is used to control the multiplexing of these pins. In an alternative embodiment, both in-system programming and boundary-scan testing are performed using the same pins and the same state machine. The test logic architecture specified in IEEE Standard 1149.1-1990 is utilized. To implement the in-system programming instructions, the instruction register of Std. 1149.1-1990 is modified to include private instructions which perform the desired programming functions.

Abstract: The disclosed structure and method route an input signal received at an input/output pin through multiple input/output cells to a routing resource. In one embodiment, each input/output cell can be programmed to provide either a combinatorial input signal or a registered input signal. Increased flexibility is achieved by routing the registered input signal or the combinatorial input signal of each cell to a routing resource via one or more I/O cells.

Abstract: A programmable logic device has multiple groups of generic logic blocks. Each group of generic logic blocks is interconnected by a local routing pools. A global routing pool is provided to interconnect the local routing pools. The global and local routing pools can be implemented in volatile or non-volatile technology, such as E.sup.2 PROM technology. The programmable logic device can also be implemented as an in-system programmable logic device.