Patents by Inventor Czeslaw Andrzej Ruszowski

Czeslaw Andrzej Ruszowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Placement of an integrated circuit
    Patent number: 7851255
    Abstract: Disclosed herein is a method of positioning and placing an integrated circuit on a printed circuit board. The integrated circuit comprises first geometrical elements. The first geometrical elements are of one or more predefined shapes and are located on one or more predefined surfaces of the integrated circuit. The printed circuit board comprises second geometrical elements. The second geometrical elements are shaped to accommodate the first geometrical elements. The first geometrical elements are designed to fit into the second geometrical elements. The first geometrical elements are positioned and placed over the second geometrical elements. The first geometrical elements come in contact with the second geometrical elements at two or more points. The positioning and placement of the first geometrical elements over the second geometrical elements limits displacement of connections of the integrated circuit from the printed circuit board.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: December 14, 2010
    Inventor: Czeslaw Andrzej Ruszowski
  • Placement Of An Integrated Circuit
    Publication number: 20100047961
    Abstract: Disclosed herein is a method of positioning and placing an integrated circuit on a printed circuit board. The integrated circuit comprises first geometrical elements. The first geometrical elements are of one or more predefined shapes and are located on one or more predefined surfaces of the integrated circuit. The printed circuit board comprises second geometrical elements. The second geometrical elements are shaped to accommodate the first geometrical elements. The first geometrical elements are designed to fit into the second geometrical elements. The first geometrical elements are positioned and placed over the second geometrical elements. The first geometrical elements come in contact with the second geometrical elements at two or more points. The positioning and placement of the first geometrical elements over the second geometrical elements limits displacement of connections of the integrated circuit from the printed circuit board.
    Type: Application
    Filed: August 21, 2008
    Publication date: February 25, 2010
    Inventor: Czeslaw Andrzej Ruszowski