Abstract: A system for handling requests that includes a set of memory banks coupled to a memory controller which comprises a set of read queues, including a read queue currently designated as the priority read queue. The memory controller loads read requests from an associated processor into the set of read queues. To process the read requests, the memory controller is configured to schedule the read requests of the priority read queue based on an availability of the associated memory bank, and if not in the priority read queue, also based on whether the read requests conflict with a recently scheduled read request from the priority read queue. Upon an execution of a read request from the priority read queue, the memory controller designates a different one of the set of read queues as the priority read queue, if the read request was at a front of the priority read queue.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

Abstract: The disclosed sterilization monitoring device comprises a perfusion channel with a chemical indicating composition disposed in fluid communication with the perfusion channel. Exposure to a sterilant creates a laterally moving front across the chemical indicating composition in the perfusion channel.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

Abstract: A fenestration unit with a first panel and a second panel, one panel being supported for sliding relative to the other. The fenestration unit includes an interpanel coupling system with a first coupling member and a second coupling member. The first coupling member includes a first facing member and a first projection that projects from the first facing member into an interpanel gap. The second coupling member includes a second facing member and a second projection that projects from the second facing member into the interpanel gap. The coupling system including a seal member that is attached to the first projection or the second projection. The seal member is configured to engage and resiliently deflect against the other of the first projection and the second projection when the second panel is in the closed position.

Abstract: A method of sealing a component assembly includes applying onto a first component a first sealant bead having, in a cross-sectional view, a first width and a first height, wherein the first width is greater than the first height. The method also includes applying over the first sealant bead a second sealant bead having, in the cross-sectional view, a second width and a second height, thereby generating a sealant stack. The second width is equal to or smaller than the second height and the second width is smaller than the first width. The method additionally includes arranging over the sealant stack a second component, such that the sealant stack is positioned between the first and second components. Furthermore, the method includes fastening the second component to the first component with the sealant stack squeezed therebetween to generate a fluid-tight seal via rheological flow of the first and second sealant beads.

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

Abstract: The load transfer system for tactical plate carriers includes a top interface, a bottom interface, and a linkage. The top interface may couple to an armor plate directly or indirectly via a plate carrier. The bottom interface may couple to anatomically inferior gear located below the top interface. The top end of the linkage may couple to the top interface and the bottom end of the linkage may couple to the bottom interface. The load transfer system may be adapted to be worn by a user to transfer a load from the user's shoulders and/or lower back to the users' hips. As a non-limiting example, the load May comprise the weight of the armor plate and/or the weight of gear suspended from the plate carrier. The load transfer system may permit movement of the armor plate relative to the anatomically inferior gear.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.

Abstract: A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.

Abstract: Welding compositions for high manganese steel base metals, the composition comprising: carbon in a range of about 0.4 wt % to about 0.8 wt %; manganese in a range of about 18 wt % to about 24 wt %; chromium in an amount of about 6 wt %; molybdenum in an amount of about <4 wt %; nickel in an amount of about <5 wt %; silicon in an amount of about 0.4 wt % to about 1.0 wt %; sulfur in an amount of about <200 ppm; phosphorus in an amount of about <200 ppm; and the balance comprising iron.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

Abstract: A method of branch prediction includes determining that a processor is to execute at least a portion of a first set of instructions. An address associated with a sequentially first instruction of the first set of instruction is determined, and a branch prediction index is determined based on the address and a branch history. A table is queried based on the branch prediction index to determine a predicted exit point of the first set of instructions. The processor fetches a subset of the first set of instructions based on the predicted exit point.

Abstract: A nanofiber filter wrap is a filter element comprising a polymer film including a first surface, a second surface opposite the first surface, an array of nanofibers extending from the first surface, a first end, a second end opposite the first end, and opposing first and second edges extending from the first end to the second end. The polymer film is wound or folded to form a plurality of spaced adjacent layers defining interlayer gaps extending through the filter element from the first edge to the second edge substantially normal to a basal plane defined by the second edge of the polymer film. A fluid flowed can be flowed through the interlayer gaps to contact at least a portion of the array of nanofibers whereby a contaminant contained in the fluid is at least partially filtered from the fluid.

Abstract: A fenestration unit with a first panel and a second panel, one panel being supported for sliding relative to the other. The fenestration unit includes an interpanel coupling system with a first coupling member and a second coupling member. The first coupling member includes a first facing member and a first projection that projects from the first facing member into an interpanel gap. The second coupling member includes a second facing member and a second projection that projects from the second facing member into the interpanel gap. The coupling system including a seal member that is attached to the first projection or the second projection. The seal member is configured to engage and resiliently deflect against the other of the first projection and the second projection when the second panel is in the closed position.

Abstract: The present application is direction to a system and method for preparing filter media from macro and nanofibers by ventilating a nanofiber media, combining the nanofiber media with macro fibers to form a hybrid media, inserting the hybrid media between a stitching plate and a stripper plate and alternatively inserting and withdrawing needles to combine the macro fibers with the nanofiber media and create a fiber web along at least one surface of the nanofiber media.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.

Abstract: A cartridge carriage and method for reducing damage to flexible circuits on fluid ejection cartridges. The carriage includes cavity therein configured to hold a fluid ejection cartridge in a fluid ejection device. The cavity includes opposing side walls attached to a front wall, a bottom wall attached to the opposing side walls perpendicular to the front wall, and a top wall distal from the bottom wall attached to the side walls and front wall. The front wall has a plurality of electrical contact pins and a first support ledge disposed apart from the electrical contact pins between the electrical contact pins and top wall. The first support ledge is configured to abut a first cartridge projection of the first fluid ejection cartridge to align the first fluid ejection cartridge with the plurality of electrical contact pins when the first fluid ejection cartridge is latched into the cartridge carriage.

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.