Abstract: A novel high-speed phase splitter circuit (100) and method of operation are disclosed. This high-speed phase splitter (100) creates a differential rail-to-rail output signal from a single ended input signal, with an inherent low skew and symmetrical output. The circuit (100) uses a phase splitting input stage (110, 130) followed by several amplification stages (150, 170) that are symmetrical and balanced in nature.

Abstract: A common (ground) of a low voltage regulator is connected to a virtual common (ground) of an integrated circuit device that is also connected to transistor sources but isolated from a true ground connected to the substrate of the integrated circuit device. The regulated output voltage from the low voltage regulator rises the same as the virtual ground voltage rises when back-biased sufficient to reduce leakage current to an acceptable level in a given process technology. Therefore, the output of the low voltage regulator will maintain a normal operating voltage for the logic during a power saving back-biased condition.

Abstract: A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link (110), such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device (120) coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.

Abstract: A novel high speed, >1 GHz or 2 Gbits/s, low voltage differential signal (LVDS) driver is disclosed. The LVDS design achieves low power consumption while providing LVDS compliant impedance termination to power supply and ground. An output stage of the LVDS is implemented using a Nmos and a Pmos follower in a push pull configuration. This new design relies first on a follower type of an output stage, which provides the inherent impedance termination, second on an AC, capacitive, coupling and DC restoration to drive output stage gates, and on a low power dummy bias generator that supplies DC restoration voltages. As the supply voltage is lower the thick oxide devices performance suffer, therefore for this new design is mainly implemented with thin oxide devices.

Abstract: A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link, such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.

Abstract: An AC electrically coupled FET device (301) is disclosed with a coupling capacitor (302) disposed for receiving a digital input signal having transitions and for AC coupling this input signal to the gate terminal of the FET device (301). A reference bias circuit (306) is provided for providing a first bias voltage (403b) that is above a threshold voltage of the FET device (301) and a second bias voltage (403a), where the first and second bias voltage (403b, 403a) are higher than rail to rail supply voltages. Switching circuitry (304, 305) is electrically coupled with the gate terminal of the FET device (301) for one of coupling of the first bias voltage (403b) and uncoupling of the second bias voltage (403a) and coupling of the second bias voltage (403a) and uncoupling of the first bias voltage (403b) in response to the transitions in the digital input signal.

Abstract: In one example embodiment involving a high-speed parallel-data communication from a first module to a second module, a termination circuit is adapted to reduce power consumption at the second module. The termination circuit includes resistive circuits respectively coupled to a plurality of parallel data-carrying lines that form the data bus. The other ends of the resistive circuits are interconnected to provide a reference voltage using the data on the parallel data-carrying lines. Consistent with one embodiment of the present invention, the communication approach uses data sets encoded so that each data set includes the same number of ones and zeroes; in this manner the reference voltage is always at midpoint and useful in providing termination to the data-carrying lines at all times.

Abstract: An ESD protection circuit is provided which offers full protection for sub micron CMOS technology integrated circuits that does not have a latchup problem as in silicon controller rectifier circuits. The primary ESD protection transistor within the circuit channeling deleterious ESD currents away from the electrical circuit using snapback conduction while additionally enabling bipolar operation of the electrical circuit.

Abstract: An ESD protection circuit is provided which offers full protection for sub micron CMOS technology integrated circuits that does not have a latchup problem as in silicon controller rectifier circuits. The primary ESD protection transistor within the circuit channeling deleterious ESD currents away from the electrical circuit using snapback conduction while additionally enabling bipolar operation of the electrical circuit.

Abstract: An approach for impedance matching a transmission line includes using the actual line impedance. According to one example embodiment, the impedance of a line connecting first and second nodes is calibrated by first driving the line to a steady-state voltage using a first current having a magnitude greater than zero, driving the current to a zero magnitude from the first node and therein inducing a voltage transient. The resultant voltage level on the line at the first node is then measured and analyzed relative to a reference voltage. The result of the comparison is then used to adjust the conductance at the second node.