Abstract: A digital processor, memory or other digital information circuit can be made compatible in a computer system which includes both 8 or 16 bit digital users within the system. The 16 bit system and local buses are divided into an upper and lower half with each half having a separate upper and lower buffer circuit respectively. A swap byte buffer is provided for selectively coupling digital information on the upper half of the local bus to the lower half of the system bus. The lower, upper, and swap byte buffers are selectively enabled in response to a discrete command signal and in the case of memory transfers, to the least significant bit of the memory address.