Abstract: A low inductance capacitor mounting structure for capacitors of multilayer printed circuit boards is provided. The capacitor mounting structure includes pads onto which a capacitor is mounted and vias or slots for connecting the solder pads to an upper conductor plane and a lower conductor plane. In the mounting structure, current is carried across the width of the solder pads so that a current in the solder pads flows directly underneath the current in the capacitor. This confinement of the magnetic filed which is between the capacitor and solder pads reduces the inductance of the associated magnetic path. The mounting structure also provides the lower conductor plane slightly below the upper conductor plane. The close spacing of the conductor planes confines a magnetic field, which is around the set of via or slot segments between the two conductor planes, so as to reduce inductance of the associated magnetic path.

Abstract: A capacitor mounting structure for printed circuit boards wherein the capacitor includes first and second terminals which are connected to first and second conductor planes in the printed circuit board. Three vias are mounted in the printed circuit board in a position to be aligned with the middle of the capacitor. A first conductor pad is mounted underneath one end of the capacitor and includes spaced apart extension portions which electrically attach to the first and third via. A second conductor pad is mounted under the other end of the capacitor and includes a central extension portion which attaches to the second or middle via. In this manner, the region available for generation of parasitic inductance is minimized thereby increasing the operating efficiency of the capacitor.

Abstract: A capacitor mounting structure for printed circuit boards wherein the capacitor includes first and second terminals which are connected to first and second conductor planes in the printed circuit board. Three vias are mounted in the printed circuit board in a position to be aligned with the middle of the capacitor. A first conductor pad is mounted underneath one end of the capacitor and includes spaced apart extension portions which electrically attach to the first and third via. A second conductor pad is mounted under the other end of the capacitor and includes a central extension portion which attaches to the second or middle via. In this manner, the region available for generation of parasitic inductance is minimized thereby increasing the operating efficiency of the capacitor.