Abstract: A multiplexor has two data inputs and three control inputs. The multiplexor is realized using two stages of three-state inverters coupled by a logic gate so as to provide a compact layout and high speed drive capability.

Abstract: A multiply/accumulate unit utilizes a fully static 32-bit arithmetic logic unit with two stage carry bypass. A four transistor carry chain places minimal loading on the chain.

Abstract: An arithmetic unit for multiplying and accumulating signed binary data and indicating an occurrence of a signed arithmetic overflow includes a multiplier-accumulator and an overflow flag register. The multiplier-accumulator receives and selectively multiples and accumulates signed binary data, and provides output data representing the multiplied and accumulated data and a sign bit representing its polarity, i.e. positive or negative. The flag register provides two "sticky" flag bits for indicating whether a signed arithmetic overflow (positive or negative) of the multiplied and accumulated data has occurred. The flag bits are "sticky" in that once a flag has been set, it cannot be reset by another arithmetic overflow condition. Instead, it must be specifically reset. The sign bit is used to selectively set one of the two sticky flag bits to a true state to indicate the direction (positive or negative) of the first arithmetic overflow.

Abstract: An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a more efficient layout. The resources of the central processing unit (CPU) are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Internal registers of the CPU are used to store pointers which reference a circular sample buffer. The CPU thus manages the selection and transfer of coefficients from the sample buffer to the multiply/accumulate unit, thereby allowing a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permitting DSP operations to be performed in parallel with CPU operations.

Abstract: The present invention provides a structured integrated circuit design methodology. The methodology is based on describing a two-phase logic function using a high level behavioral description flow chart, properly sizing devices to be used in the circuit for speed and reducing trial and error in circuit layout implementation using novel chip planning techniques. The methodology begins with the definition of signal types based on the circuit function that creates a particular signal and the type of input signal that feeds the circuit function. A rigid set of rules is then established for use of the signal types. Next the technical specification of the two-phase logic function is defined and utilized to create a behavioral flow chart using defined symbols. An associated database of corresponding Boolean equations is then created that defines the parameters of the various elements of the flow chart.

Abstract: An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms.