Patents by Inventor Da Chang

Da Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015054
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Application
    Filed: September 18, 2024
    Publication date: January 9, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Yu-Ting XUE, Ching-Hung TSENG, Guan-Hua LU, Hong-Da CHANG
  • Publication number: 20250008706
    Abstract: The invention provides an AC/DC conversion device for intelligent green-power operation and maintenance in power transmission and transformation projects, including a cabinet, an assembling panel, an inverter, a driving mechanism and a controller. A door is mounted at the front portion of the cabinet in a fixed and sealed manner, and the assembling panel is fixedly mounted on the back wall of the cabinet inside the cabinet. The assembling panel, the inverter, the driving mechanism and the controller are all provided inside the cabinet, which provides desirable dust-proof effects, preventing the case where the inverter, the driving mechanism and the controller are interfered by the dust, so that this device is suitable for outdoor usage. The driving mechanism and the controller work in coordination, so that the inverter can be switched off in time when it burns out and smokes, thereby substantially reducing the risk of fire hazards.
    Type: Application
    Filed: March 20, 2024
    Publication date: January 2, 2025
    Inventors: Chengjia BAO, Long ZHAO, Ru LIU, Xushan HAN, Yanhong MA, Chen LIANG, Qiang ZHOU, Hailong GUO, Tianyi ZHANG, Wei NIU, Weicheng SHEN, Hui YUAN, Wenyuan BAI, Kequan LIU, Qingzhao HU, Ziqiang GUO, Guohan MA, Da CHANG, Bo WU, Li WANG, Yanhua DOU, Yechang GAO, Qin LIANG, Shuzhen REN
  • Patent number: 12184194
    Abstract: The invention provides an AC/DC conversion device for intelligent green-power operation and maintenance in power transmission and transformation projects, including a cabinet, an assembling panel, an inverter, a driving mechanism and a controller. A door is mounted at the front portion of the cabinet in a fixed and sealed manner, and the assembling panel is fixedly mounted on the back wall of the cabinet inside the cabinet. The assembling panel, the inverter, the driving mechanism and the controller are all provided inside the cabinet, which provides desirable dust-proof effects, preventing the case where the inverter, the driving mechanism and the controller are interfered by the dust, so that this device is suitable for outdoor usage. The driving mechanism and the controller work in coordination, so that the inverter can be switched off in time when it burns out and smokes, thereby substantially reducing the risk of fire hazards.
    Type: Grant
    Filed: March 20, 2024
    Date of Patent: December 31, 2024
    Assignees: STATE GRID GANSU ELECTRIC POWER COMPANY LANZHOU POWER SUPPLY COMPANY, STATE GRID GANSU ELECTRIC POWER RESEARCH INSTITUTE
    Inventors: Chengjia Bao, Long Zhao, Ru Liu, Xushan Han, Yanhong Ma, Chen Liang, Qiang Zhou, Hailong Guo, Tianyi Zhang, Wei Niu, Weicheng Shen, Hui Yuan, Wenyuan Bai, Kequan Liu, Qingzhao Hu, Ziqiang Guo, Guohan Ma, Da Chang, Bo Wu, Li Wang, Yanhua Dou, Yechang Gao, Qin Liang, Shuzhen Ren
  • Patent number: 12159567
    Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.
    Type: Grant
    Filed: September 14, 2023
    Date of Patent: December 3, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ying-Da Chang, Chulho Choi, Yu-Chieh Huang, Ching-Chieh Wu, Hajoon Shin, Zhen-Guo Ding, Jia-Way Chen, Kyunlyeol Lee, Yongjoo Song
  • Patent number: 12125828
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: October 22, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20240233609
    Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.
    Type: Application
    Filed: September 14, 2023
    Publication date: July 11, 2024
    Inventors: Ying-Da Chang, Chulho Choi, Yu-Chieh Huang, Ching-Chieh Wu, Hajoon Shin, Zhen-Guo Ding, Jia-Way Chen, Kyunlyeol Lee, Yongjoo Song
  • Publication number: 20240135859
    Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.
    Type: Application
    Filed: September 13, 2023
    Publication date: April 25, 2024
    Inventors: Ying-Da Chang, Chulho Choi, Yu-Chieh Huang, Ching-Chieh Wu, Hajoon Shin, Zhen-Guo Ding, Jia-Way Chen, Kyunlyeol Lee, Yongjoo Song
  • Patent number: 11923337
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 5, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20230420420
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Yu-Ting XUE, Ching-Hung TSENG, Guan-Hua LU, Hong-Da CHANG
  • Patent number: 11676877
    Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: June 13, 2023
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Chun-Chang Ting, Chi-Jen Chen
  • Patent number: 11600571
    Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: March 7, 2023
    Assignee: Siliconware Precision Industries Co., Ltd
    Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
  • Publication number: 20220278013
    Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Chun-Chang Ting, Chi-Jen Chen
  • Patent number: 11398413
    Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: July 26, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Chun-Chang Ting, Chi-Jen Chen
  • Patent number: 11307160
    Abstract: The present disclosure relates to a welding quality detecting field, and specifically relates to a quality detection device. The quality detection device includes an integrated probe set, a driving module and a collecting module. The integrated probe set includes a plurality of integrated probe assemblies. The integrated probe assemblies are disposed in pairs and each integrated probe assembly includes a driving end and a collecting end. The driving end of one integrated probe assembly is matched with the driving end of another integrated probe assembly disposed in pairs with the one integrated probe assembly. The collecting end of one integrated probe assembly is matched with the collecting end of another integrated probe assembly disposed in pairs with the one integrated probe assembly.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: April 19, 2022
    Assignee: HAN'S LASER TECHNOLOGY INDUSTRY GROUP CO., LTD
    Inventors: Sheng Lin Wang, Hao Liu, Da Chang Hu, Yong Hu, Peng Fei Lei, Ji Guo Liu, Zuo Bin Xu, Yun Feng Gao
  • Publication number: 20210104465
    Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.
    Type: Application
    Filed: December 17, 2020
    Publication date: April 8, 2021
    Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
  • Publication number: 20210074603
    Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.
    Type: Application
    Filed: January 6, 2020
    Publication date: March 11, 2021
    Inventors: Hong-Da Chang, Chun-Chang Ting, Chi-Jen Chen
  • Patent number: 10942590
    Abstract: A display device includes: a substrate including a plurality of pixel regions; a first electrode arranged on each of the pixel regions of the substrate; an organic layer arranged on the first electrode; a second electrode including a plurality of second electrode patterns each at least partially overlapping respective ones of the pixel regions and arranged on the organic layer; and a plurality of sensing lines spaced apart from the first electrode on the same plane or layer as the first electrode, the sensing lines being connected to respective ones of the second electrode patterns.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: March 9, 2021
    Inventors: Jong Han Jeong, Ha Da Chang, Hyoung Wook Jang
  • Patent number: 10903167
    Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 26, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
  • Publication number: 20200350285
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Application
    Filed: August 29, 2019
    Publication date: November 5, 2020
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20200249189
    Abstract: The present disclosure relates to a welding quality detecting field, and specifically relates to a quality detection device. The quality detection device includes an integrated probe set, a driving module and a collecting module. The integrated probe set includes a plurality of integrated probe assemblies. The integrated probe assemblies are disposed in pairs and each integrated probe assembly includes a driving end and a collecting end. The driving end of one integrated probe assembly is matched with the driving end of another integrated probe assembly disposed in pairs with the one integrated probe assembly. The collecting end of one integrated probe assembly is matched with the collecting end of another integrated probe assembly disposed in pairs with the one integrated probe assembly.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: SHENG LIN WANG, HAO LIU, DA CHANG HU, YONG HU, PENG FEI LEI, JI GUO LIU, ZUO BIN XU, YUN FENG GAO