Abstract: A method for transmitting data between a processor and a storage medium includes receiving data from the processor and acquiring identifier information of the data. The storage medium queries a start address based on the identifier information. A specified storage block corresponding to the data is set as a target storage block, and a target control module is set based on the specified data operation. The target control module with a pointer pointing at the start address transmits the data sections of the data. When an interrupt command is received and the pointed-to address is an end address, an output function of the storage medium is disabled to maintain integrity of the data while transmitting. An apparatus and a storage medium applying the method are also disclosed.

Abstract: An integrated reduced media independent interface (Integrated RMII) and related method for interconnecting a MAC Circuit and a PHY Circuit. The Integrated RMII comprises a TXD, a TX_EN, a REF_CLK, a CRS_DV, and a RXD as essentially specified in the IEEE 802.3 and IEEE 802.3u specifications. The CRS_DV is at a predetermined low potential in an error-detection mode and an idle mode, and at a predetermined high potential in a transmission mode. When the CRS_DV is at the predetermined low potential, the MAC Circuit can reject data transmitted from the PHY Circuit via the RXD. When the CRS_DV is at the predetermined high potential, the MAC Circuit can receive the data transmitted from the PHY Circuit via the RXD.

Abstract: An integrated reduced media independent interface (Integrated RMII) and related method for interconnecting a MAC Circuit and a PHY Circuit. The Integrated RMII comprises a TXD, a TX_EN, a REF_CLK, a CRS_DV, and a RXD as essentially specified in the IEEE 802.3 and IEEE 802.3u specifications. The CRS_DV is at a predetermined low potential in an error-detection mode and an idle mode, and at a predetermined high potential in a transmission mode. When the CRS_DV is at the predetermined low potential, the MAC Circuit can reject data transmitted from the PHY Circuit via the RXD. When the CRS_DV is at the predetermined high potential, the MAC Circuit can receive the data transmitted from the PHY Circuit via the RXD.

Abstract: A signal display apparatus has a plurality of shift registers and a selecting circuit. The shift registers receives a first clock and the selecting circuit receives a selecting signal from a data flow according to a second clock, and output enabling signals to the shift registers according to the selecting signal. The shift registers selectively store data in the data flow according to the first clock in response to the enabling signals. The signal display apparatus and the method for storing data are capable of reducing the transfer time for a serial data single series signal to overcome the prior art shortcomings.

Abstract: A signal display apparatus has a plurality of shift registers and a selecting circuit. The shift registers receives a first clock and the selecting circuit receives a selecting signal from a data flow according to a second clock, and output enabling signals to the shift registers according to the selecting signal. The shift registers selectively store data in the data flow according to the first clock in response to the enabling signals. The signal display apparatus and the method for storing data are capable of reducing the transfer time for a serial data single series signal to overcome the prior art shortcomings.