Patents by Inventor Da Hee Kim
Da Hee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963423Abstract: A transparent display device comprises: a first substrate including a display area and first to fourth bezel areas surrounding the display area, wherein the display area includes a plurality of pixel regions each including an emitting portion and a transparent portion; a second substrate facing the first substrate; a transparent dam between the first and second substrates and in the first to fourth bezel areas; a first pad electrode on the first substrate and in the first bezel area; and a first color filter pattern on the second substrate and in the first bezel area.Type: GrantFiled: June 3, 2021Date of Patent: April 16, 2024Assignee: LG DISPLAY CO., LTD.Inventors: Da-Woon Jeong, Su-Yeon Lee, Sung-Hee Kim, Jae-Bin Song, Sung-Hee Park
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ANODE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY INCLUDING THE SAME
Publication number: 20240120465Abstract: An anode active material for a secondary battery includes a carbon-based active material, and silicon-based active material particles doped with magnesium. At least some of the silicon-based active material particles include pores, and a volume ratio of pores having a diameter of 50 nm or less among the pores is 2% or less based on a total volume of the silicon-based active material particles.Type: ApplicationFiled: September 7, 2023Publication date: April 11, 2024Inventors: Hwan Ho JANG, Moon Sung KIM, Hyo Mi KIM, Sang Baek RYU, Da Hye PARK, Eun Jun PARK, Seung Hyun YOOK, Da Bin CHUNG, Jun Hee HAN -
Publication number: 20240097104Abstract: The technology and implementations disclosed in this patent document generally relate to a lithium secondary battery including: a first unit cell including a first anode including a 1-1 anode mixture layer and a 1-2 anode mixture layer on the 1-1 anode mixture layer, and a second unit cell including a second anode including a 2-1 anode mixture layer and a 2-2 anode mixture layer on the 2-1 anode mixture layer, wherein a weight ratio of the silicon-based active material in the 1-2 anode mixture layer is greater than a weight ratio of the silicon-based active material in the 1-1 anode mixture layer, and a weight ratio of the silicon-based active material in the 2-2 anode mixture layer is less than or equal to a weight ratio of the silicon-based active material in the 2-1 anode mixture layer.Type: ApplicationFiled: August 2, 2023Publication date: March 21, 2024Inventors: Jun Hee HAN, Moon Sung KIM, Hyo Mi KIM, Sang Baek RYU, Da Hye PARK, Sang In BANG, Seung Hyun YOOK, Hwan Ho JANG, Da Bin CHUNG
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Patent number: 11932618Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.Type: GrantFiled: March 13, 2023Date of Patent: March 19, 2024Assignee: ILDONG PHARMACEUTICAL CO., LTD.Inventors: Hong Chul Yoon, Kyung Mi An, Myong Jae Lee, Jin Hee Lee, Jeong-geun Kim, A-rang Im, Woo Jin Jeon, Jin Ah Jeong, Jaeho Heo, Changhee Hong, Kyeojin Kim, Jung-Eun Park, Te-ik Sohn, Changmok Oh, Da Hae Hong, Sung Wook Kwon, Jung Ho Kim, Jae Eui Shin, Yeongran Yoo, Min Whan Chang, Eun Hye Jang, In-gyu Je, Ji Hye Choi, Gunhee Kim, Yearin Jun
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Patent number: 11929491Abstract: An anode for a lithium secondary battery includes an anode current collector, and an anode active material layer formed on at least one surface of the anode current collector. The anode active material layer includes a carbon-based active material, a first silicon-based active material doped with magnesium and a second silicon-based active material not doped with magnesium. A content of the first silicon-based active material is in a range from 2 wt % to 20 wt % based on a total weight of the anode active material layer.Type: GrantFiled: June 6, 2023Date of Patent: March 12, 2024Assignee: SK ON CO., LTD.Inventors: Hwan Ho Jang, Moon Sung Kim, Hyo Mi Kim, Sang Baek Ryu, Da Hye Park, Seung Hyun Yook, Da Bin Chung, Jun Hee Han
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Patent number: 11929495Abstract: In some implementations, the anode includes a current collector, a first anode mixture layer formed on at least one surface of the current collector, and a second anode mixture layer formed on the first anode mixture layer. The first anode mixture layer and the second anode mixture layer include a carbon-based active material, respectively. The first anode mixture layer includes a first binder, a first silicon-based active material, and a first conductive material. The second anode mixture layer includes a second binder, a second silicon-based active material, and a second conductive material. Contents of the first conductive material and the second conductive material are different from each other with respect to the total combined weight of the first anode mixture layer and the second anode mixture layer. Types of the first silicon-based active material and the second silicon-based active material are different from each other.Type: GrantFiled: May 18, 2023Date of Patent: March 12, 2024Assignee: SK ON CO., LTD.Inventors: Hyo Mi Kim, Moon Sung Kim, Sang Baek Ryu, Da Hye Park, Seung Hyun Yook, Hwan Ho Jang, Kwang Ho Jeong, Da Bin Chung, Jun Hee Han
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Publication number: 20230330005Abstract: Disclosed is a self-assembled complex containing a calcium ion that includes a calcium ion; and at least one ligand, where the calcium ion and the ligand participate in a reversibly self-assembly or self-disassembly. The shape of the self-assembled complex varies depending on the type of the ligand, or the mixing ratio of the ligand when there are a plurality of ligands.Type: ApplicationFiled: November 18, 2022Publication date: October 19, 2023Applicant: Korea University Research and Business FoundationInventors: Heemin KANG, Sung-Gue LEE, Na-Yeon KANG, Yu-Ri KIM, Gun-Hyu BAE, Da-Hee KIM, Seong-Yeol KIM
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Patent number: 11121066Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and a heat dissipation layer embedded in the encapsulant so that one surface thereof is exposed. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip.Type: GrantFiled: November 14, 2019Date of Patent: September 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Da Hee Kim, Young Gwan Ko, Sung Won Jeong
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Patent number: 10872863Abstract: A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.Type: GrantFiled: December 11, 2018Date of Patent: December 22, 2020Assignee: SAMSUNG ELECTRONICS CO.. LTD.Inventors: Joo Young Choi, Doo Hwan Lee, Da Hee Kim, Jae Hoon Choi, Byung Ho Kim
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Patent number: 10770418Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; a resin layer disposed on the encapsulant; and a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant, wherein the resin layer covers at least portions of the exposed one surface of the rear redistribution layer, and the rear redistribution layer is electrically connected to the redistribution layer of the first connection member through connection members formed in first openings penetrating through the resin layer and the encapsulant.Type: GrantFiled: March 9, 2018Date of Patent: September 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Da Hee Kim, Young Gwan Ko
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Patent number: 10692805Abstract: A semiconductor package includes a semiconductor chip having a first surface on which connection pads are disposed and a second surface opposing the first surface; a connection member including a first insulating layer disposed on the first surface of the semiconductor chip, a wiring pattern disposed on the first insulating layer and having a top surface of which an edge is rounded, a via penetrating through the first insulating layer and electrically connecting the connection pads to the wiring pattern, and a second insulating layer disposed on the first insulating layer and covering the wiring pattern; and an encapsulant disposed on the connection member and encapsulating the semiconductor chip.Type: GrantFiled: October 25, 2018Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Da Hee Kim
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Patent number: 10622273Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.Type: GrantFiled: June 12, 2018Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joo Young Choi, Joon Sung Kim, Young Min Kim, Da Hee Kim, Tae Wook Kim, Byung Ho Kim
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Publication number: 20200091054Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and a heat dissipation layer embedded in the encapsulant so that one surface thereof is exposed. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip.Type: ApplicationFiled: November 14, 2019Publication date: March 19, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD,Inventors: Da Hee Kim, Young Gwan KO, Sung Won JEONG
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Publication number: 20200075492Abstract: A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.Type: ApplicationFiled: December 11, 2018Publication date: March 5, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joo Young CHOI, Doo Hwan LEE, Da Hee KIM, Jae Hoon CHOI, Byung Ho KIM
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Patent number: 10573613Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; a resin layer disposed on the encapsulant; and a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant, wherein the resin layer covers at least portions of the exposed one surface of the rear redistribution layer, and the rear redistribution layer is electrically connected to the redistribution layer of the first connection member through connection members formed in first openings penetrating through the resin layer and the encapsulant.Type: GrantFiled: January 12, 2017Date of Patent: February 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Da Hee Kim, Young Gwan Ko
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Patent number: 10522451Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and a heat dissipation layer embedded in the encapsulant so that one surface thereof is exposed. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip.Type: GrantFiled: July 13, 2018Date of Patent: December 31, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Da Hee Kim, Young Gwan Ko, Sung Won Jeong
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Patent number: 10403583Abstract: A fan-out semiconductor package includes: a semiconductor chip; a first connection member including a plurality of redistribution layers and one or more layer of vias; an encapsulant; and a second connection member, wherein the encapsulant has first openings exposing at least portions of the first connection member, the first connection member has second openings exposing at least portions of a redistribution layer disposed at an uppermost portion among the plurality of redistribution layers, at least portions of the first openings and the second openings overlap each other, and a content of a metal constituting the plurality of redistribution layers and the one or more layer of vias is higher in a lower portion of the first connection member than in an upper portion of the first connection member.Type: GrantFiled: March 28, 2018Date of Patent: September 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Da Hee Kim
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Patent number: 10402620Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.Type: GrantFiled: May 16, 2018Date of Patent: September 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung Ho Kim, Da Hee Kim, Joon Sung Kim, Joo Young Choi, Hee Sook Park, Tae Wook Kim
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Publication number: 20190206783Abstract: A semiconductor package includes a semiconductor chip having a first surface on which connection pads are disposed and a second surface opposing the first surface; a connection member including a first insulating layer disposed on the first surface of the semiconductor chip, a wiring pattern disposed on the first insulating layer and having a top surface of which an edge is rounded, a via penetrating through the first insulating layer and electrically connecting the connection pads to the wiring pattern, and a second insulating layer disposed on the first insulating layer and covering the wiring pattern; and an encapsulant disposed on the connection member and encapsulating the semiconductor chip.Type: ApplicationFiled: October 25, 2018Publication date: July 4, 2019Inventor: Da Hee KIM
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Publication number: 20190206755Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.Type: ApplicationFiled: June 12, 2018Publication date: July 4, 2019Inventors: Joo Young CHOI, Joon Sung KIM, Young Min KIM, Da Hee KIM, Tae Wook KIM, Byung Ho KIM