Patents by Inventor Da-Jun Lin

Da-Jun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210143324
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, part of the MTJ stack is removed, a first cap layer is formed on a sidewall of the MTJ stack, and the first cap layer and the MTJ stack are removed to form a first MTJ and a second MTJ.
    Type: Application
    Filed: December 9, 2019
    Publication date: May 13, 2021
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Shih-Wei Su, Ting-An Chien
  • Publication number: 20210119110
    Abstract: A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Ting-An Chien
  • Patent number: 10978339
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai
  • Publication number: 20210074917
    Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.
    Type: Application
    Filed: October 1, 2019
    Publication date: March 11, 2021
    Inventors: Shih-Wei Su, Da-Jun Lin, Bin-Siang Tsai, Ya-Jyuan Hung, Ting-An Chien
  • Publication number: 20210050511
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a magnetic tunneling junction (MTJ) on the metal interconnection; forming a top electrode on the MTJ; and forming a trapping layer on the top electrode for trapping hydrogen. Preferably, the trapping layer includes a concentration gradient, in which a concentration of hydrogen decreases from a top surface of the top electrode toward the MTJ.
    Type: Application
    Filed: September 8, 2019
    Publication date: February 18, 2021
    Inventors: Da-Jun Lin, Tai-Cheng Hou, Bin-Siang Tsai, Ting-An Chien
  • Publication number: 20200395413
    Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part . The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.
    Type: Application
    Filed: July 17, 2019
    Publication date: December 17, 2020
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Ya-Jyuan Hung, Chin-Chia Yang, Ting-An Chien
  • Patent number: 10847465
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, San-Fu Lin
  • Publication number: 20200266095
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
  • Publication number: 20200227354
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, San-Fu Lin
  • Patent number: 10692758
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 23, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
  • Publication number: 20200185325
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 11, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, San-Fu Lin
  • Publication number: 20200185264
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 11, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
  • Publication number: 20200185629
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer; performing a treatment process to rough a top surface of the first metal interconnection; and forming a carbon nanotube (CNT) junction on the first metal interconnection. Preferably, the treatment process further includes forming protrusions on the top surface of the first metal interconnection, in which the protrusions and the first metal interconnection comprise same material.
    Type: Application
    Filed: January 8, 2019
    Publication date: June 11, 2020
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Chin-Chia Yang
  • Patent number: 10665546
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 26, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Da-jun Lin, Bin-Siang Tsai, San-Fu Lin
  • Publication number: 20190355618
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.
    Type: Application
    Filed: June 18, 2018
    Publication date: November 21, 2019
    Inventors: Da-Jun Lin, Bin-Siang Tsai