Abstract: A semiconductor structure with a silicon through via (TSV) includes a semiconductor substrate. A TSV penetrates the semiconductor substrate. The TSV includes a metal layer, a barrier layer and an isolation layer. An end of the metal layer protrudes from a back side of the semiconductor substrate. A recess is disposed at one side of the end of the metal layer. A composite structure fills the recess. The composite structure includes a thermal conductive layer and a first dielectric layer. The thermal conductive layer contacts the sidewall of the end of the metal layer and contacts the barrier layer, the isolation layer and the semiconductor substrate. A first dielectric layer is disposed on the thermal conductive layer. A top surface of the first dielectric layer is aligned with the end of the metal layer. The thermal conductive layer includes aluminum nitride, aluminum oxide or diamond.

Abstract: A semiconductor structure includes a semiconductor substrate, pad structures, dielectric structures, a second dielectric layer, and a void. The semiconductor substrate includes a first dielectric layer, the pad structures and the dielectric structure are disposed on the first dielectric layer, and each dielectric structure is disposed on a sidewall of one of the pad structures. A top surface of each dielectric structure is lower than a top surface of each pad structure in a vertical direction. The first dielectric layer includes a recess located between two adjacent dielectric structures in a horizontal direction. The second dielectric layer covers the pad structures, the dielectric structures, and the first dielectric layer. The void is located in the second dielectric layer. At least a part of the void is sandwiched between two adjacent pad structures in the horizontal direction, and the void is located directly above the recess in the vertical direction.

Abstract: A semiconductor structure includes an SOI substrate having a base substrate, a buried oxide layer on the base substrate, and a device layer on the buried oxide layer, a circuit element disposed on the device layer and surrounded by a trench isolation region in the SOI substrate; an etch stop layer disposed around the circuit element; a first dielectric layer disposed on the etch stop layer; and a buried power rail embedded in the first dielectric layer, the etch stop layer, the trench isolation region, and the buried oxide layer. The buried power rail is isolated from the device layer through the buried oxide layer and trench-filling oxide in the trench isolation region.

Abstract: An interposer includes a substrate having an inductor forming region thereon, a plurality of trenches within the inductor forming region in the substrate, a buffer layer lining interior surfaces of the plurality of trenches and forming air gaps within the plurality of trenches, and an inductor coil pattern embedded in the buffer layer within the inductor forming region.

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, a silicon-rich tensile stress layer, a passivation layer, an ultraviolet (UV)-transparent protection layer, a gate structure, a source structure, and a drain structure. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. The passivation layer is disposed on the silicon-rich tensile stress layer. The UV-transparent protection layer is disposed on the passivation layer. The gate structure penetrates through the UV-transparent protection layer, the passivation layer, and the silicon-rich tensile stress layer. The gate structure is partly disposed in the silicon-doped III-V compound barrier layer.

Abstract: A semiconductor structure includes a SOI substrate having a base substrate, a buried oxide layer on the base substrate, and a device layer on the buried oxide layer. A circuit element is disposed on the device layer and surrounded by a trench isolation region in the SOI substrate. A buried power rail is embedded in the trench isolation region and the buried oxide layer. The buried power rail is isolated from the device layer by the buried oxide layer and a trench-filling oxide in the trench isolation region.

Abstract: The invention provides a semiconductor structure comprising a resistive random access memory (RRAM) and a double capacitor. The semiconductor structure includes a substrate, wherein a cell region and a capacitor region are defined on the substrate, and the resistive random access memory is located in the cell region, wherein the RRAM comprises a variable resistance layer, and a double capacitor structure is located in the capacitor region, wherein the double capacitor structure comprises a lower capacitor structure and an upper capacitor structure, and the material of a first high dielectric constant layer in the lower capacitor structure is the same as the material of the variable resistance layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element and a lower silicide element between the metal element and the channel layer. The lower silicide element has a hydrogen content less than 2 at %.

Abstract: The invention provides a semiconductor structure with magnetic tunnel junction (MTJ) and inductor. The semiconductor structure comprising a substrate, a cell region and an inductor region defined on the substrate, a magnetic tunnel junction (MTJ) is located in the cell region, wherein the MTJ comprises a first MTJ material layer. And an inductor is located in the inductor region, wherein the inductor comprises a multi-layer structure, the multi-layer structure comprises at least one second MTJ material layer, wherein the material of the first MTJ material layer is the same as that of the second MTJ material layer, and viewed from a sectional view, the first MTJ material layer extends along a horizontal direction, and the second MTJ material layer comprises a horizontal part and two vertical parts, and the vertical part extends along a vertical direction.

Abstract: A method for forming ohmic contacts on a compound semiconductor device is disclosed. A channel layer is formed on a substrate. A barrier layer is formed on the channel layer. A passivation layer is formed on the barrier layer. A contact area is formed by etching through the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A sacrificial metallic layer is conformally deposited on the contact area. The sacrificial metallic layer is subjected to an annealing process, thereby forming a heavily doped region in the channel layer directly under the sacrificial metallic layer. The sacrificial metallic layer is removed to expose the heavily doped region. A metal silicide layer is formed on the heavily doped region.

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A silicon-rich tensile stress layer is formed on the III-V compound barrier layer. An annealing process is performed after the silicon-rich tensile stress layer is formed. A part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process.

Abstract: A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.

Abstract: A structure with an MRAM and an inductor includes a first dielectric layer. A second dielectric layer covers the first dielectric layer. Numerous second metal lines are embedded in the first dielectric layer. An MRAM is disposed between the second dielectric layer and the first dielectric layer. A magnetic core is disposed below the second dielectric layer and covers the second metal lines. The distance from the topmost surface of the magnetic core to the first dielectric layer is smaller than the distance from the topmost surface of the MRAM to the first dielectric layer. Numerous fourth metal lines are embedded in the second dielectric layer and disposed on the magnetic core. The fourth metal lines and the second metal lines are electrically connected through numerous first conductive plugs. The second metal lines, the fourth metal lines and the first conductive plugs form an inductor coil surrounding the magnetic core.

Abstract: An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a passivation layer, a source doped region, a drain doped region, a source electrode, a drain electrode, a source silicide layer, a drain silicide layer, and a gate electrode. A silicon concentration of a second region of the passivation layer is higher than that of a first region under the second region. The source doped region and the drain doped region are disposed in the III-V compound semiconductor layer. The source electrode and the drain electrode are disposed on the source doped region and the drain doped region, respectively. The source silicide layer is disposed between the source electrode and the source doped region. The drain silicide layer is disposed between the drain electrode and the drain doped region. The source silicide layer and the drain silicide layer are further disposed partly on the passivation layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element and a lower silicide element between the metal element and the channel layer. The lower silicide element has a hydrogen content less than 2 at %.

Abstract: A capacitor structure includes a substrate. A recess is disposed in the substrate, wherein the recess includes a sidewall and a bottom. A pillar is disposed in the recess and contacts the bottom of the recess. The pillar is formed by stacking a silicon nitride-based material layer and a silicon oxide-based material layer cyclically and alternately. The silicon oxide-based material layer includes a first sidewall. The first sidewall is arc-shaped. An MIM capacitor continuously covers and contacts the pillar, the sidewall of the recess and the bottom of the recess.

Abstract: A capacitor structure includes a dielectric stack structure, a bottom electrode, a top electrode, and a capacitor dielectric layer. The dielectric stack structure is disposed on a substrate and includes a stop layer and a dielectric layer disposed on the stop layer. The bottom electrode is disposed in the dielectric stack structure. The top electrode is disposed above the substrate. The bottom electrode surrounds the top electrode in a horizontal direction. The capacitor dielectric layer is disposed between the bottom electrode and the top electrode. The bottom electrode includes a first dual damascene structure surrounding the capacitor dielectric layer and the top electrode in the horizontal direction. An upper portion of the first dual damascene structure is disposed in the dielectric layer. A lower portion of the first dual damascene structure is partly disposed in the dielectric layer. The lower portion penetrates through the stop layer in a vertical direction.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A passivation layer is formed on the III-V compound barrier layer. A silicon layer is formed on the passivation layer, the III-V compound barrier layer, and the III-V compound semiconductor layer. A silicon implantation process is performed to the III-V compound semiconductor layer for forming a source doped region and a drain doped region in the III-V compound semiconductor layer under the silicon layer. A source electrode and a drain electrode are formed on the silicon layer. A source silicide layer is formed between the source electrode and the source doped region, and a drain silicide layer is formed between the drain electrode and the drain doped region. The source silicide layer and the drain silicide layer are partly formed on the passivation layer.

Abstract: A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.