Abstract: The present disclosure provides a flat panel detection substrate, a fabricating method thereof and a flat panel detector. The flat panel detection substrate according to the present disclosure includes a base substrate; a bias electrode and a sense electrode on the base substrate; and a semiconductor layer over the bias electrode and the sense electrode, the semiconductor layer having a thickness greater than 100 nm.

Abstract: A substrate processing method performed in a chamber of a substrate processing apparatus is provided. The chamber includes a substrate support, an upper electrode, and a gas supply port. The substrate processing method includes (a) providing the substrate on the substrate support; (b) supplying a first processing gas into the chamber; (c) continuously supplying an RF signal into the chamber while continuously supplying a negative DC voltage to the upper electrode, to generate plasma from the first processing gas in the chamber; and (d) supplying a pulsed RF signal while continuously supplying the negative DC voltage to the upper electrode, to generate plasma from the first processing gas in the chamber. The process further includes repeating alternately repeating the steps (c) and (d), and a time for performing the step (c) once is 30 second or shorter.

Abstract: A flat panel detector includes a base substrate, a sensing electrode and a bias electrode over the base substrate, and an insulating layer over the sensing electrode and the bias electrode at a side distal from the substrate. A difference between thicknesses of regions of the insulating layer corresponding to the sensing electrode and the bias electrode respectively is not greater than a preset threshold. When a sufficiently high voltage is applied to the insulating layer and turned on, because the thickness thereof is relatively uniform, a dark current generated by the sensing electrode and the bias electrode under the insulating layer is relatively uniform, thereby improving detection accuracy of the flat panel detector.

Abstract: A flat panel detector includes a base substrate, a sensing electrode and a bias electrode over the base substrate, and an insulating layer over the sensing electrode and the bias electrode at a side distal from the substrate. A difference between thicknesses of regions of the insulating layer corresponding to the sensing electrode and the bias electrode respectively is not greater than a preset threshold. When a sufficiently high voltage is applied to the insulating layer and turned on, because the thickness thereof is relatively uniform, a dark current generated by the sensing electrode and the bias electrode under the insulating layer is relatively uniform, thereby improving detection accuracy of the flat panel detector.

Abstract: A substrate processing method performed in a chamber of a substrate processing apparatus is provided. The chamber includes a substrate support, an upper electrode, and a gas supply port. The substrate processing method includes (a) providing the substrate on the substrate support; (b) supplying a first processing gas into the chamber; (c) continuously supplying an RF signal into the chamber while continuously supplying a negative DC voltage to the upper electrode, to generate plasma from the first processing gas in the chamber; and (d) supplying a pulsed RF signal while continuously supplying the negative DC voltage to the upper electrode, to generate plasma from the first processing gas in the chamber. The process further includes repeating alternately repeating the steps (c) and (d), and a time for performing the step (c) once is 30 second or shorter.

Abstract: The present disclosure provides a flat panel detection substrate, a fabricating method thereof and a flat panel detector. The flat panel detection substrate according to the present disclosure includes a base substrate; a bias electrode and a sense electrode on the base substrate; and a semiconductor layer over the bias electrode and the sense electrode, the semiconductor layer having a thickness greater than 100 nm.

Abstract: An etching method using a remote plasma source (RPS) and a method of fabricating a semiconductor device, the etching method including generating a plasma by supplying a process gas to at least one RPS and applying power to the at least one RPS; and etching a first material film including SiNx by supplying the plasma and at least one control gas selected from HBr, HCl, HI, NH3, SiH4, CHF3, and CH2F2 to a process chamber.

Abstract: An etching method using a remote plasma source (RPS) and a method of fabricating a semiconductor device, the etching method including generating a plasma by supplying a process gas to at least one RPS and applying power to the at least one RPS; and etching a first material film including SiNx by supplying the plasma and at least one control gas selected from HBr, HCl, HI, NH3, SiH4, CHF3, and CH2F2 to a process chamber.

Abstract: A wafer clamping apparatus, including a plurality of support pins under a wafer, the plurality of pins to support the wafer; and a side clamp at a lateral side of the wafer, the side clamp to directly contact a lateral side of the wafer to press the wafer, the side clamp to press the wafer in a first direction or a second direction, the first direction and the second direction being different directions.

Abstract: A wafer clamping apparatus, including a plurality of support pins under a wafer, the plurality of pins to support the wafer; and a side clamp at a lateral side of the wafer, the side clamp to directly contact a lateral side of the wafer to press the wafer, the side clamp to press the wafer in a first direction or a second direction, the first direction and the second direction being different directions.

Abstract: The present invention relates to a macro instruction set computer (MISC) architecture having main memory for storing system softwares of the computer, instructions, and user programs; first memory for storing preparatory data for operations, intermediate results of operations and the final results of completed operations, and operating in stack form; second memory for storing the break point address of subprograms and address for recovery of the break point while returning from a call, and operating in stack form; a CPU having: address management for the main memory; main memory data port for receiving instructions and data from main memory and writing data in the CPU into main memory; control logic combinational decoding for decoding instructions from main memory and generating control signals controlling the operations of the computer; ALU for performing arithmetic and logic operation functions; top of stack, next to the top of stack and the third one to the top of stack register of the first memory; top of