Abstract: A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on an N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending area and a second lengthwise-extending area connected to a right end of the transverse-extending area. A first P-type body is formed in the N-type layer, and overlaps the left periphery of the first lengthwise-extending area of the gate layer. A second P-type body is formed in the N-type layer, and overlaps the right periphery of the second lengthwise-extending area of the gate layer.

Abstract: A chip structure including an integrated circuit (IC) element, a plurality of bumps and at least one spacer is provided. The IC element has a plurality of contacts. The bumps are disposed on the contacts respectively. The spacer is disposed on the IC element and between two of the bumps adjacent to each other, and the thickness of the spacer is less than or equal to that of the bumps. Through the arrangement of the spacer, the two bumps are well insulated from each other. Furthermore, a manufacturing process of the chip structure and a chip package with the chip structure are also provided.

Abstract: A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on an N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending area and a second lengthwise-extending area connected to a right end of the transverse-extending area. A first P-type body is formed in the N-type layer, and overlaps the left periphery of the first lengthwise-extending area of the gate layer. A second P-type body is formed in the N-type layer, and overlaps the right periphery of the second lengthwise-extending area of the gate layer.

Abstract: A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on a N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending area and a second lengthwise-extending area connected to a right end of the transverse-extending area. A first P-type body is formed in the N-type layer, and overlaps the left periphery of the first lengthwise-extending area of the gate layer. A second P-type body is formed in the N-type layer, and overlaps the right periphery of the second lengthwise-extending area of the gate layer.

Abstract: A method of reducing substrate step height. The method includes providing a substrate having a low-voltage device area and high-voltage device area divided by an isolation structure, forming an oxidation mask at least approximately 500 ? thick over the low-voltage device area and parts of the isolation structure, forming a first oxide layer on the exposed high-voltage device area and isolation structure using the oxidation mask as a mask, removing the oxidation mask, and forming a second oxide layer, thinner than the first oxide layer, on the low-voltage device layer.

Abstract: A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on a N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending area and a second lengthwise-extending area connected to a right end of the transverse-extending area. A first P-type body is formed in the N-type layer, and overlaps the left periphery of the first lengthwise-extending area of the gate layer. A second P-type body is formed in the N-type layer, and overlaps the right periphery of the second lengthwise-extending area of the gate layer.