Patents by Inventor Da Qiang YU

Da Qiang YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10062704
    Abstract: A method is provided for fabricating a buried-channel MOSFET and a surface-channel MOSFET of the same type and different gate electrodes on a same wafer. The method includes providing a semiconductor substrate having a well area and a plurality of shallow trench isolation structures; forming a threshold implantation region doped with impurity ions opposite of that of the well area in the well area for the buried-channel MOSFET; forming a gate structure including a gate dielectric layer and a gate electrode on the semiconductor substrate, wherein the gate electrode of the buried-channel MOSFET is doped with impurity ions with a same type as that of the well area, and the gate electrode of the surface-channel MOSFET is doped with impurity ions with a type opposite of that of the well area; and forming source and drain regions in the semiconductor substrate at both sides of the gate structure.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 28, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Tzu Yin Chiu, Clifford Ian Drowley, Leong Tee Koh, Yu Lei Jiang, Da Qiang Yu
  • Publication number: 20170194339
    Abstract: A method is provided for fabricating a buried-channel MOSFET and a surface-channel MOSFET of the same type and different gate electrodes on a same wafer. The method includes providing a semiconductor substrate having a well area and a plurality of shallow trench isolation structures; forming a threshold implantation region doped with impurity ions opposite of that of the well area in the well area for the buried-channel MOSFET; forming a gate structure including a gate dielectric layer and a gate electrode on the semiconductor substrate, wherein the gate electrode of the buried-channel MOSFET is doped with impurity ions with a same type as that of the well area, and the gate electrode of the surface-channel MOSFET is doped with impurity ions with a type opposite of that of the well area; and forming source and drain regions in the semiconductor substrate at both sides of the gate structure.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 6, 2017
    Inventors: Tzu Yin CHIU, Clifford Ian DROWLEY, Leong Tee KOH, Yu Lei JIANG, Da Qiang YU